1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_85xx.h> 28 #include <asm/immap_fsl_pci.h> 29 #include <asm/io.h> 30 #include <spd_sdram.h> 31 #include <miiphy.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 35 #include "../common/pixis.h" 36 37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 38 extern void ddr_enable_ecc(unsigned int dram_size); 39 #endif 40 41 void sdram_init(void); 42 43 int checkboard (void) 44 { 45 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 46 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 47 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); 48 49 if ((uint)&gur->porpllsr != 0xe00e0000) { 50 printf("immap size error %x\n",&gur->porpllsr); 51 } 52 printf ("Board: MPC8544DS\n"); 53 54 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 55 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 56 ecm->eedr = 0xffffffff; /* Clear ecm errors */ 57 ecm->eeer = 0xffffffff; /* Enable ecm errors */ 58 59 return 0; 60 } 61 62 phys_size_t 63 initdram(int board_type) 64 { 65 long dram_size = 0; 66 67 puts("Initializing\n"); 68 69 dram_size = spd_sdram(); 70 71 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 72 /* 73 * Initialize and enable DDR ECC. 74 */ 75 ddr_enable_ecc(dram_size); 76 #endif 77 puts(" DDR: "); 78 return dram_size; 79 } 80 81 #ifdef CONFIG_PCI1 82 static struct pci_controller pci1_hose; 83 #endif 84 85 #ifdef CONFIG_PCIE1 86 static struct pci_controller pcie1_hose; 87 #endif 88 89 #ifdef CONFIG_PCIE2 90 static struct pci_controller pcie2_hose; 91 #endif 92 93 #ifdef CONFIG_PCIE3 94 static struct pci_controller pcie3_hose; 95 #endif 96 97 int first_free_busno=0; 98 99 void 100 pci_init_board(void) 101 { 102 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 103 uint devdisr = gur->devdisr; 104 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 105 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 106 107 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 108 devdisr, io_sel, host_agent); 109 110 if (io_sel & 1) { 111 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 112 printf (" eTSEC1 is in sgmii mode.\n"); 113 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 114 printf (" eTSEC3 is in sgmii mode.\n"); 115 } 116 117 #ifdef CONFIG_PCIE3 118 { 119 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; 120 extern void fsl_pci_init(struct pci_controller *hose); 121 struct pci_controller *hose = &pcie3_hose; 122 int pcie_ep = (host_agent == 1); 123 int pcie_configured = io_sel >= 1; 124 125 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 126 printf ("\n PCIE3 connected to ULI as %s (base address %x)", 127 pcie_ep ? "End Point" : "Root Complex", 128 (uint)pci); 129 if (pci->pme_msg_det) { 130 pci->pme_msg_det = 0xffffffff; 131 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 132 } 133 printf ("\n"); 134 135 /* inbound */ 136 pci_set_region(hose->regions + 0, 137 CFG_PCI_MEMORY_BUS, 138 CFG_PCI_MEMORY_PHYS, 139 CFG_PCI_MEMORY_SIZE, 140 PCI_REGION_MEM | PCI_REGION_MEMORY); 141 142 /* outbound memory */ 143 pci_set_region(hose->regions + 1, 144 CFG_PCIE3_MEM_BASE, 145 CFG_PCIE3_MEM_PHYS, 146 CFG_PCIE3_MEM_SIZE, 147 PCI_REGION_MEM); 148 149 /* outbound io */ 150 pci_set_region(hose->regions + 2, 151 CFG_PCIE3_IO_BASE, 152 CFG_PCIE3_IO_PHYS, 153 CFG_PCIE3_IO_SIZE, 154 PCI_REGION_IO); 155 156 hose->region_count = 3; 157 #ifdef CFG_PCIE3_MEM_BASE2 158 /* outbound memory */ 159 pci_set_region(hose->regions + 3, 160 CFG_PCIE3_MEM_BASE2, 161 CFG_PCIE3_MEM_PHYS2, 162 CFG_PCIE3_MEM_SIZE2, 163 PCI_REGION_MEM); 164 hose->region_count++; 165 #endif 166 hose->first_busno=first_free_busno; 167 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 168 169 fsl_pci_init(hose); 170 171 first_free_busno=hose->last_busno+1; 172 printf (" PCIE3 on bus %02x - %02x\n", 173 hose->first_busno,hose->last_busno); 174 175 /* 176 * Activate ULI1575 legacy chip by performing a fake 177 * memory access. Needed to make ULI RTC work. 178 */ 179 in_be32((u32 *)CFG_PCIE3_MEM_BASE); 180 } else { 181 printf (" PCIE3: disabled\n"); 182 } 183 184 } 185 #else 186 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 187 #endif 188 189 #ifdef CONFIG_PCIE1 190 { 191 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 192 extern void fsl_pci_init(struct pci_controller *hose); 193 struct pci_controller *hose = &pcie1_hose; 194 int pcie_ep = (host_agent == 5); 195 int pcie_configured = io_sel & 6; 196 197 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 198 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", 199 pcie_ep ? "End Point" : "Root Complex", 200 (uint)pci); 201 if (pci->pme_msg_det) { 202 pci->pme_msg_det = 0xffffffff; 203 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 204 } 205 printf ("\n"); 206 207 /* inbound */ 208 pci_set_region(hose->regions + 0, 209 CFG_PCI_MEMORY_BUS, 210 CFG_PCI_MEMORY_PHYS, 211 CFG_PCI_MEMORY_SIZE, 212 PCI_REGION_MEM | PCI_REGION_MEMORY); 213 214 /* outbound memory */ 215 pci_set_region(hose->regions + 1, 216 CFG_PCIE1_MEM_BASE, 217 CFG_PCIE1_MEM_PHYS, 218 CFG_PCIE1_MEM_SIZE, 219 PCI_REGION_MEM); 220 221 /* outbound io */ 222 pci_set_region(hose->regions + 2, 223 CFG_PCIE1_IO_BASE, 224 CFG_PCIE1_IO_PHYS, 225 CFG_PCIE1_IO_SIZE, 226 PCI_REGION_IO); 227 228 hose->region_count = 3; 229 #ifdef CFG_PCIE1_MEM_BASE2 230 /* outbound memory */ 231 pci_set_region(hose->regions + 3, 232 CFG_PCIE1_MEM_BASE2, 233 CFG_PCIE1_MEM_PHYS2, 234 CFG_PCIE1_MEM_SIZE2, 235 PCI_REGION_MEM); 236 hose->region_count++; 237 #endif 238 hose->first_busno=first_free_busno; 239 240 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 241 242 fsl_pci_init(hose); 243 244 first_free_busno=hose->last_busno+1; 245 printf(" PCIE1 on bus %02x - %02x\n", 246 hose->first_busno,hose->last_busno); 247 248 } else { 249 printf (" PCIE1: disabled\n"); 250 } 251 252 } 253 #else 254 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 255 #endif 256 257 #ifdef CONFIG_PCIE2 258 { 259 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; 260 extern void fsl_pci_init(struct pci_controller *hose); 261 struct pci_controller *hose = &pcie2_hose; 262 int pcie_ep = (host_agent == 3); 263 int pcie_configured = io_sel & 4; 264 265 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 266 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", 267 pcie_ep ? "End Point" : "Root Complex", 268 (uint)pci); 269 if (pci->pme_msg_det) { 270 pci->pme_msg_det = 0xffffffff; 271 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 272 } 273 printf ("\n"); 274 275 /* inbound */ 276 pci_set_region(hose->regions + 0, 277 CFG_PCI_MEMORY_BUS, 278 CFG_PCI_MEMORY_PHYS, 279 CFG_PCI_MEMORY_SIZE, 280 PCI_REGION_MEM | PCI_REGION_MEMORY); 281 282 /* outbound memory */ 283 pci_set_region(hose->regions + 1, 284 CFG_PCIE2_MEM_BASE, 285 CFG_PCIE2_MEM_PHYS, 286 CFG_PCIE2_MEM_SIZE, 287 PCI_REGION_MEM); 288 289 /* outbound io */ 290 pci_set_region(hose->regions + 2, 291 CFG_PCIE2_IO_BASE, 292 CFG_PCIE2_IO_PHYS, 293 CFG_PCIE2_IO_SIZE, 294 PCI_REGION_IO); 295 296 hose->region_count = 3; 297 #ifdef CFG_PCIE2_MEM_BASE2 298 /* outbound memory */ 299 pci_set_region(hose->regions + 3, 300 CFG_PCIE2_MEM_BASE2, 301 CFG_PCIE2_MEM_PHYS2, 302 CFG_PCIE2_MEM_SIZE2, 303 PCI_REGION_MEM); 304 hose->region_count++; 305 #endif 306 hose->first_busno=first_free_busno; 307 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 308 309 fsl_pci_init(hose); 310 first_free_busno=hose->last_busno+1; 311 printf (" PCIE2 on bus %02x - %02x\n", 312 hose->first_busno,hose->last_busno); 313 314 } else { 315 printf (" PCIE2: disabled\n"); 316 } 317 318 } 319 #else 320 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 321 #endif 322 323 324 #ifdef CONFIG_PCI1 325 { 326 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 327 extern void fsl_pci_init(struct pci_controller *hose); 328 struct pci_controller *hose = &pci1_hose; 329 330 uint pci_agent = (host_agent == 6); 331 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 332 uint pci_32 = 1; 333 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 334 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 335 336 337 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 338 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 339 (pci_32) ? 32 : 64, 340 (pci_speed == 33333000) ? "33" : 341 (pci_speed == 66666000) ? "66" : "unknown", 342 pci_clk_sel ? "sync" : "async", 343 pci_agent ? "agent" : "host", 344 pci_arb ? "arbiter" : "external-arbiter", 345 (uint)pci 346 ); 347 348 /* inbound */ 349 pci_set_region(hose->regions + 0, 350 CFG_PCI_MEMORY_BUS, 351 CFG_PCI_MEMORY_PHYS, 352 CFG_PCI_MEMORY_SIZE, 353 PCI_REGION_MEM | PCI_REGION_MEMORY); 354 355 /* outbound memory */ 356 pci_set_region(hose->regions + 1, 357 CFG_PCI1_MEM_BASE, 358 CFG_PCI1_MEM_PHYS, 359 CFG_PCI1_MEM_SIZE, 360 PCI_REGION_MEM); 361 362 /* outbound io */ 363 pci_set_region(hose->regions + 2, 364 CFG_PCI1_IO_BASE, 365 CFG_PCI1_IO_PHYS, 366 CFG_PCI1_IO_SIZE, 367 PCI_REGION_IO); 368 hose->region_count = 3; 369 #ifdef CFG_PCIE3_MEM_BASE2 370 /* outbound memory */ 371 pci_set_region(hose->regions + 3, 372 CFG_PCIE3_MEM_BASE2, 373 CFG_PCIE3_MEM_PHYS2, 374 CFG_PCIE3_MEM_SIZE2, 375 PCI_REGION_MEM); 376 hose->region_count++; 377 #endif 378 hose->first_busno=first_free_busno; 379 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 380 381 fsl_pci_init(hose); 382 first_free_busno=hose->last_busno+1; 383 printf ("PCI on bus %02x - %02x\n", 384 hose->first_busno,hose->last_busno); 385 } else { 386 printf (" PCI: disabled\n"); 387 } 388 } 389 #else 390 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 391 #endif 392 } 393 394 395 int last_stage_init(void) 396 { 397 return 0; 398 } 399 400 401 unsigned long 402 get_board_sys_clk(ulong dummy) 403 { 404 u8 i, go_bit, rd_clks; 405 ulong val = 0; 406 407 go_bit = in8(PIXIS_BASE + PIXIS_VCTL); 408 go_bit &= 0x01; 409 410 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); 411 rd_clks &= 0x1C; 412 413 /* 414 * Only if both go bit and the SCLK bit in VCFGEN0 are set 415 * should we be using the AUX register. Remember, we also set the 416 * GO bit to boot from the alternate bank on the on-board flash 417 */ 418 419 if (go_bit) { 420 if (rd_clks == 0x1c) 421 i = in8(PIXIS_BASE + PIXIS_AUX); 422 else 423 i = in8(PIXIS_BASE + PIXIS_SPD); 424 } else { 425 i = in8(PIXIS_BASE + PIXIS_SPD); 426 } 427 428 i &= 0x07; 429 430 switch (i) { 431 case 0: 432 val = 33333333; 433 break; 434 case 1: 435 val = 40000000; 436 break; 437 case 2: 438 val = 50000000; 439 break; 440 case 3: 441 val = 66666666; 442 break; 443 case 4: 444 val = 83000000; 445 break; 446 case 5: 447 val = 100000000; 448 break; 449 case 6: 450 val = 133333333; 451 break; 452 case 7: 453 val = 166666666; 454 break; 455 } 456 457 return val; 458 } 459 460 #if defined(CONFIG_OF_BOARD_SETUP) 461 462 void 463 ft_board_setup(void *blob, bd_t *bd) 464 { 465 int node, tmp[2]; 466 const char *path; 467 468 ft_cpu_setup(blob, bd); 469 470 node = fdt_path_offset(blob, "/aliases"); 471 tmp[0] = 0; 472 if (node >= 0) { 473 #ifdef CONFIG_PCI1 474 path = fdt_getprop(blob, node, "pci0", NULL); 475 if (path) { 476 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 477 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 478 } 479 #endif 480 #ifdef CONFIG_PCIE2 481 path = fdt_getprop(blob, node, "pci1", NULL); 482 if (path) { 483 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; 484 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 485 } 486 #endif 487 #ifdef CONFIG_PCIE1 488 path = fdt_getprop(blob, node, "pci2", NULL); 489 if (path) { 490 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 491 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 492 } 493 #endif 494 #ifdef CONFIG_PCIE3 495 path = fdt_getprop(blob, node, "pci3", NULL); 496 if (path) { 497 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; 498 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 499 } 500 #endif 501 } 502 } 503 #endif 504