1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <pci.h> 11 #include <asm/processor.h> 12 #include <asm/mmu.h> 13 #include <asm/immap_85xx.h> 14 #include <fsl_ddr_sdram.h> 15 #include <ioports.h> 16 #include <spd_sdram.h> 17 #include <libfdt.h> 18 #include <fdt_support.h> 19 20 #include "../common/cadmus.h" 21 #include "../common/eeprom.h" 22 #include "../common/via.h" 23 24 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 25 extern void ddr_enable_ecc(unsigned int dram_size); 26 #endif 27 28 void local_bus_init(void); 29 30 /* 31 * I/O Port configuration table 32 * 33 * if conf is 1, then that port pin will be configured at boot time 34 * according to the five values podr/pdir/ppar/psor/pdat for that entry 35 */ 36 37 const iop_conf_t iop_conf_tab[4][32] = { 38 39 /* Port A configuration */ 40 { /* conf ppar psor pdir podr pdat */ 41 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ 42 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ 43 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ 44 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ 45 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ 46 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ 47 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ 48 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ 49 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ 50 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ 51 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ 52 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ 53 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ 54 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ 55 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ 56 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ 57 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ 58 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ 59 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ 60 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ 61 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ 62 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ 63 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ 64 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ 65 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ 66 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ 67 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ 68 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ 69 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ 70 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ 71 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ 72 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ 73 }, 74 75 /* Port B configuration */ 76 { /* conf ppar psor pdir podr pdat */ 77 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ 78 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ 79 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ 80 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ 81 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ 82 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ 83 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ 84 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ 85 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ 86 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ 87 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ 88 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ 89 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ 90 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ 91 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ 92 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ 93 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ 94 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ 95 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ 96 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ 97 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 98 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 99 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 100 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 101 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 102 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 103 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 104 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 105 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 106 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 107 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 108 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ 109 }, 110 111 /* Port C */ 112 { /* conf ppar psor pdir podr pdat */ 113 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ 114 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ 115 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ 116 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ 117 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ 118 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ 119 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ 120 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ 121 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ 122 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ 123 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ 124 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ 125 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ 126 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ 127 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ 128 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ 129 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ 130 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ 131 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ 132 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ 133 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ 134 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ 135 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ 136 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ 137 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ 138 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ 139 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ 140 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ 141 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ 142 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ 143 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ 144 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ 145 }, 146 147 /* Port D */ 148 { /* conf ppar psor pdir podr pdat */ 149 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ 150 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ 151 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ 152 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ 153 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ 154 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ 155 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ 156 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ 157 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ 158 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ 159 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ 160 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ 161 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ 162 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ 163 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ 164 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ 165 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ 166 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ 167 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ 168 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ 169 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ 170 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ 171 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ 172 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ 173 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ 174 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ 175 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ 176 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ 177 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 178 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 179 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 180 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ 181 } 182 }; 183 184 int checkboard (void) 185 { 186 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 187 char buf[32]; 188 189 /* PCI slot in USER bits CSR[6:7] by convention. */ 190 uint pci_slot = get_pci_slot (); 191 192 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 193 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ 194 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ 195 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ 196 197 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 198 199 uint cpu_board_rev = get_cpu_board_revision (); 200 201 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", 202 get_board_version (), pci_slot); 203 204 printf ("CPU Board Revision %d.%d (0x%04x)\n", 205 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), 206 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); 207 208 printf("PCI1: %d bit, %s MHz, %s\n", 209 (pci1_32) ? 32 : 64, 210 strmhz(buf, pci1_speed), 211 pci1_clk_sel ? "sync" : "async"); 212 213 if (pci_dual) { 214 printf("PCI2: 32 bit, 66 MHz, %s\n", 215 pci2_clk_sel ? "sync" : "async"); 216 } else { 217 printf("PCI2: disabled\n"); 218 } 219 220 /* 221 * Initialize local bus. 222 */ 223 local_bus_init (); 224 225 return 0; 226 } 227 228 /* 229 * Initialize Local Bus 230 */ 231 void 232 local_bus_init(void) 233 { 234 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 235 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 236 237 uint clkdiv; 238 uint lbc_hz; 239 sys_info_t sysinfo; 240 uint temp_lbcdll; 241 242 /* 243 * Errata LBC11. 244 * Fix Local Bus clock glitch when DLL is enabled. 245 * 246 * If localbus freq is < 66MHz, DLL bypass mode must be used. 247 * If localbus freq is > 133MHz, DLL can be safely enabled. 248 * Between 66 and 133, the DLL is enabled with an override workaround. 249 */ 250 251 get_sys_info(&sysinfo); 252 clkdiv = lbc->lcrr & LCRR_CLKDIV; 253 lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; 254 255 if (lbc_hz < 66) { 256 lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ 257 258 } else if (lbc_hz >= 133) { 259 lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ 260 261 } else { 262 lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ 263 udelay(200); 264 265 /* 266 * Sample LBC DLL ctrl reg, upshift it to set the 267 * override bits. 268 */ 269 temp_lbcdll = gur->lbcdllcr; 270 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); 271 asm("sync;isync;msync"); 272 } 273 } 274 275 /* 276 * Initialize SDRAM memory on the Local Bus. 277 */ 278 void lbc_sdram_init(void) 279 { 280 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 281 282 uint idx; 283 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 284 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 285 uint cpu_board_rev; 286 uint lsdmr_common; 287 288 puts("LBC SDRAM: "); 289 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, 290 "\n "); 291 292 /* 293 * Setup SDRAM Base and Option Registers 294 */ 295 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 296 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 297 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 298 asm("msync"); 299 300 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 301 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 302 asm("msync"); 303 304 /* 305 * Determine which address lines to use baed on CPU board rev. 306 */ 307 cpu_board_rev = get_cpu_board_revision(); 308 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 309 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { 310 lsdmr_common |= LSDMR_BSMA1617; 311 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { 312 lsdmr_common |= LSDMR_BSMA1516; 313 } else { 314 /* 315 * Assume something unable to identify itself is 316 * really old, and likely has lines 16/17 mapped. 317 */ 318 lsdmr_common |= LSDMR_BSMA1617; 319 } 320 321 /* 322 * Issue PRECHARGE ALL command. 323 */ 324 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 325 asm("sync;msync"); 326 *sdram_addr = 0xff; 327 ppcDcbf((unsigned long) sdram_addr); 328 udelay(100); 329 330 /* 331 * Issue 8 AUTO REFRESH commands. 332 */ 333 for (idx = 0; idx < 8; idx++) { 334 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 335 asm("sync;msync"); 336 *sdram_addr = 0xff; 337 ppcDcbf((unsigned long) sdram_addr); 338 udelay(100); 339 } 340 341 /* 342 * Issue 8 MODE-set command. 343 */ 344 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 345 asm("sync;msync"); 346 *sdram_addr = 0xff; 347 ppcDcbf((unsigned long) sdram_addr); 348 udelay(100); 349 350 /* 351 * Issue NORMAL OP command. 352 */ 353 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 354 asm("sync;msync"); 355 *sdram_addr = 0xff; 356 ppcDcbf((unsigned long) sdram_addr); 357 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 358 359 #endif /* enable SDRAM init */ 360 } 361 362 #if defined(CONFIG_PCI) 363 /* For some reason the Tundra PCI bridge shows up on itself as a 364 * different device. Work around that by refusing to configure it. 365 */ 366 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 367 368 static struct pci_config_table pci_mpc85xxcds_config_table[] = { 369 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 370 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 371 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 372 mpc85xx_config_via_usbide, {0,0,0}}, 373 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 374 mpc85xx_config_via_usb, {0,0,0}}, 375 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 376 mpc85xx_config_via_usb2, {0,0,0}}, 377 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 378 mpc85xx_config_via_power, {0,0,0}}, 379 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 380 mpc85xx_config_via_ac97, {0,0,0}}, 381 {}, 382 }; 383 384 static struct pci_controller hose[] = { 385 { config_table: pci_mpc85xxcds_config_table,}, 386 #ifdef CONFIG_MPC85XX_PCI2 387 {}, 388 #endif 389 }; 390 391 #endif /* CONFIG_PCI */ 392 393 void 394 pci_init_board(void) 395 { 396 #ifdef CONFIG_PCI 397 pci_mpc85xx_init(hose); 398 #endif 399 } 400 401 #if defined(CONFIG_OF_BOARD_SETUP) 402 void 403 ft_pci_setup(void *blob, bd_t *bd) 404 { 405 int node, tmp[2]; 406 const char *path; 407 408 node = fdt_path_offset(blob, "/aliases"); 409 tmp[0] = 0; 410 if (node >= 0) { 411 #ifdef CONFIG_PCI1 412 path = fdt_getprop(blob, node, "pci0", NULL); 413 if (path) { 414 tmp[1] = hose[0].last_busno - hose[0].first_busno; 415 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 416 } 417 #endif 418 #ifdef CONFIG_MPC85XX_PCI2 419 path = fdt_getprop(blob, node, "pci1", NULL); 420 if (path) { 421 tmp[1] = hose[1].last_busno - hose[1].first_busno; 422 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 423 } 424 #endif 425 } 426 } 427 #endif 428