1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/immap_85xx.h> 29 #include <ioports.h> 30 #include <spd_sdram.h> 31 #include <libfdt.h> 32 #include <fdt_support.h> 33 34 #include "../common/cadmus.h" 35 #include "../common/eeprom.h" 36 #include "../common/via.h" 37 38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 39 extern void ddr_enable_ecc(unsigned int dram_size); 40 #endif 41 42 void local_bus_init(void); 43 void sdram_init(void); 44 45 /* 46 * I/O Port configuration table 47 * 48 * if conf is 1, then that port pin will be configured at boot time 49 * according to the five values podr/pdir/ppar/psor/pdat for that entry 50 */ 51 52 const iop_conf_t iop_conf_tab[4][32] = { 53 54 /* Port A configuration */ 55 { /* conf ppar psor pdir podr pdat */ 56 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ 57 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ 58 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ 59 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ 60 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ 61 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ 62 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ 63 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ 64 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ 65 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ 66 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ 67 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ 68 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ 69 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ 70 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ 71 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ 72 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ 73 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ 74 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ 75 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ 76 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ 77 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ 78 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ 79 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ 80 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ 81 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ 82 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ 83 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ 84 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ 85 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ 86 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ 87 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ 88 }, 89 90 /* Port B configuration */ 91 { /* conf ppar psor pdir podr pdat */ 92 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ 93 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ 94 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ 95 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ 96 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ 97 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ 98 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ 99 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ 100 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ 101 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ 102 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ 103 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ 104 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ 105 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ 106 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ 107 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ 108 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ 109 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ 110 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ 111 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ 112 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 113 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 114 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 115 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ 116 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 117 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 118 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 119 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ 120 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 121 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 122 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 123 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ 124 }, 125 126 /* Port C */ 127 { /* conf ppar psor pdir podr pdat */ 128 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ 129 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ 130 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ 131 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ 132 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ 133 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ 134 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ 135 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ 136 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ 137 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ 138 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ 139 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ 140 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ 141 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ 142 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ 143 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ 144 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ 145 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ 146 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ 147 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ 148 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ 149 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ 150 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ 151 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ 152 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ 153 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ 154 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ 155 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ 156 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ 157 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ 158 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ 159 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ 160 }, 161 162 /* Port D */ 163 { /* conf ppar psor pdir podr pdat */ 164 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ 165 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ 166 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ 167 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ 168 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ 169 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ 170 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ 171 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ 172 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ 173 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ 174 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ 175 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ 176 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ 177 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ 178 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ 179 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ 180 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ 181 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ 182 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ 183 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ 184 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ 185 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ 186 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ 187 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ 188 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ 189 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ 190 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ 191 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ 192 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 193 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 194 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ 195 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ 196 } 197 }; 198 199 int board_early_init_f (void) 200 { 201 return 0; 202 } 203 204 int checkboard (void) 205 { 206 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 207 208 /* PCI slot in USER bits CSR[6:7] by convention. */ 209 uint pci_slot = get_pci_slot (); 210 211 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 212 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ 213 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ 214 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ 215 216 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 217 218 uint cpu_board_rev = get_cpu_board_revision (); 219 220 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", 221 get_board_version (), pci_slot); 222 223 printf ("CPU Board Revision %d.%d (0x%04x)\n", 224 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), 225 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); 226 227 printf (" PCI1: %d bit, %s MHz, %s\n", 228 (pci1_32) ? 32 : 64, 229 (pci1_speed == 33000000) ? "33" : 230 (pci1_speed == 66000000) ? "66" : "unknown", 231 pci1_clk_sel ? "sync" : "async"); 232 233 if (pci_dual) { 234 printf (" PCI2: 32 bit, 66 MHz, %s\n", 235 pci2_clk_sel ? "sync" : "async"); 236 } else { 237 printf (" PCI2: disabled\n"); 238 } 239 240 /* 241 * Initialize local bus. 242 */ 243 local_bus_init (); 244 245 return 0; 246 } 247 248 long int 249 initdram(int board_type) 250 { 251 long dram_size = 0; 252 253 puts("Initializing\n"); 254 255 #if defined(CONFIG_DDR_DLL) 256 { 257 /* 258 * Work around to stabilize DDR DLL MSYNC_IN. 259 * Errata DDR9 seems to have been fixed. 260 * This is now the workaround for Errata DDR11: 261 * Override DLL = 1, Course Adj = 1, Tap Select = 0 262 */ 263 264 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 265 266 gur->ddrdllcr = 0x81000000; 267 asm("sync;isync;msync"); 268 udelay(200); 269 } 270 #endif 271 dram_size = spd_sdram(); 272 273 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 274 /* 275 * Initialize and enable DDR ECC. 276 */ 277 ddr_enable_ecc(dram_size); 278 #endif 279 /* 280 * SDRAM Initialization 281 */ 282 sdram_init(); 283 284 puts(" DDR: "); 285 return dram_size; 286 } 287 288 /* 289 * Initialize Local Bus 290 */ 291 void 292 local_bus_init(void) 293 { 294 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 295 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 296 297 uint clkdiv; 298 uint lbc_hz; 299 sys_info_t sysinfo; 300 uint temp_lbcdll; 301 302 /* 303 * Errata LBC11. 304 * Fix Local Bus clock glitch when DLL is enabled. 305 * 306 * If localbus freq is < 66Mhz, DLL bypass mode must be used. 307 * If localbus freq is > 133Mhz, DLL can be safely enabled. 308 * Between 66 and 133, the DLL is enabled with an override workaround. 309 */ 310 311 get_sys_info(&sysinfo); 312 clkdiv = lbc->lcrr & 0x0f; 313 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 314 315 if (lbc_hz < 66) { 316 lbc->lcrr |= 0x80000000; /* DLL Bypass */ 317 318 } else if (lbc_hz >= 133) { 319 lbc->lcrr &= (~0x80000000); /* DLL Enabled */ 320 321 } else { 322 lbc->lcrr &= (~0x8000000); /* DLL Enabled */ 323 udelay(200); 324 325 /* 326 * Sample LBC DLL ctrl reg, upshift it to set the 327 * override bits. 328 */ 329 temp_lbcdll = gur->lbcdllcr; 330 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); 331 asm("sync;isync;msync"); 332 } 333 } 334 335 /* 336 * Initialize SDRAM memory on the Local Bus. 337 */ 338 void 339 sdram_init(void) 340 { 341 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) 342 343 uint idx; 344 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 345 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 346 uint cpu_board_rev; 347 uint lsdmr_common; 348 349 puts(" SDRAM: "); 350 351 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 352 353 /* 354 * Setup SDRAM Base and Option Registers 355 */ 356 lbc->or2 = CFG_OR2_PRELIM; 357 asm("msync"); 358 359 lbc->br2 = CFG_BR2_PRELIM; 360 asm("msync"); 361 362 lbc->lbcr = CFG_LBC_LBCR; 363 asm("msync"); 364 365 366 lbc->lsrt = CFG_LBC_LSRT; 367 lbc->mrtpr = CFG_LBC_MRTPR; 368 asm("msync"); 369 370 /* 371 * Determine which address lines to use baed on CPU board rev. 372 */ 373 cpu_board_rev = get_cpu_board_revision(); 374 lsdmr_common = CFG_LBC_LSDMR_COMMON; 375 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { 376 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; 377 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { 378 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; 379 } else { 380 /* 381 * Assume something unable to identify itself is 382 * really old, and likely has lines 16/17 mapped. 383 */ 384 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; 385 } 386 387 /* 388 * Issue PRECHARGE ALL command. 389 */ 390 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; 391 asm("sync;msync"); 392 *sdram_addr = 0xff; 393 ppcDcbf((unsigned long) sdram_addr); 394 udelay(100); 395 396 /* 397 * Issue 8 AUTO REFRESH commands. 398 */ 399 for (idx = 0; idx < 8; idx++) { 400 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; 401 asm("sync;msync"); 402 *sdram_addr = 0xff; 403 ppcDcbf((unsigned long) sdram_addr); 404 udelay(100); 405 } 406 407 /* 408 * Issue 8 MODE-set command. 409 */ 410 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; 411 asm("sync;msync"); 412 *sdram_addr = 0xff; 413 ppcDcbf((unsigned long) sdram_addr); 414 udelay(100); 415 416 /* 417 * Issue NORMAL OP command. 418 */ 419 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; 420 asm("sync;msync"); 421 *sdram_addr = 0xff; 422 ppcDcbf((unsigned long) sdram_addr); 423 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 424 425 #endif /* enable SDRAM init */ 426 } 427 428 #if defined(CFG_DRAM_TEST) 429 int 430 testdram(void) 431 { 432 uint *pstart = (uint *) CFG_MEMTEST_START; 433 uint *pend = (uint *) CFG_MEMTEST_END; 434 uint *p; 435 436 printf("Testing DRAM from 0x%08x to 0x%08x\n", 437 CFG_MEMTEST_START, 438 CFG_MEMTEST_END); 439 440 printf("DRAM test phase 1:\n"); 441 for (p = pstart; p < pend; p++) 442 *p = 0xaaaaaaaa; 443 444 for (p = pstart; p < pend; p++) { 445 if (*p != 0xaaaaaaaa) { 446 printf ("DRAM test fails at: %08x\n", (uint) p); 447 return 1; 448 } 449 } 450 451 printf("DRAM test phase 2:\n"); 452 for (p = pstart; p < pend; p++) 453 *p = 0x55555555; 454 455 for (p = pstart; p < pend; p++) { 456 if (*p != 0x55555555) { 457 printf ("DRAM test fails at: %08x\n", (uint) p); 458 return 1; 459 } 460 } 461 462 printf("DRAM test passed.\n"); 463 return 0; 464 } 465 #endif 466 467 #if defined(CONFIG_PCI) 468 /* For some reason the Tundra PCI bridge shows up on itself as a 469 * different device. Work around that by refusing to configure it. 470 */ 471 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 472 473 static struct pci_config_table pci_mpc85xxcds_config_table[] = { 474 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 475 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 476 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 477 mpc85xx_config_via_usbide, {0,0,0}}, 478 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 479 mpc85xx_config_via_usb, {0,0,0}}, 480 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 481 mpc85xx_config_via_usb2, {0,0,0}}, 482 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 483 mpc85xx_config_via_power, {0,0,0}}, 484 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 485 mpc85xx_config_via_ac97, {0,0,0}}, 486 {}, 487 }; 488 489 static struct pci_controller hose[] = { 490 { config_table: pci_mpc85xxcds_config_table,}, 491 #ifdef CONFIG_MPC85XX_PCI2 492 {}, 493 #endif 494 }; 495 496 #endif /* CONFIG_PCI */ 497 498 void 499 pci_init_board(void) 500 { 501 #ifdef CONFIG_PCI 502 pci_mpc85xx_init(hose); 503 #endif 504 } 505 506 #if defined(CONFIG_OF_BOARD_SETUP) 507 void 508 ft_pci_setup(void *blob, bd_t *bd) 509 { 510 int node, tmp[2]; 511 const char *path; 512 513 node = fdt_path_offset(blob, "/aliases"); 514 tmp[0] = 0; 515 if (node >= 0) { 516 #ifdef CONFIG_PCI1 517 path = fdt_getprop(blob, node, "pci0", NULL); 518 if (path) { 519 tmp[1] = hose[0].last_busno - hose[0].first_busno; 520 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 521 } 522 #endif 523 #ifdef CONFIG_MPC85XX_PCI2 524 path = fdt_getprop(blob, node, "pci1", NULL); 525 if (path) { 526 tmp[1] = hose[1].last_busno - hose[1].first_busno; 527 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 528 } 529 #endif 530 } 531 } 532 #endif 533