1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/mmu.h> 12 13 struct fsl_e_tlb_entry tlb_table[] = { 14 /* TLB 0 - for temp stack in cache */ 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 16 MAS3_SX|MAS3_SW|MAS3_SR, 0, 17 0, 0, BOOKE_PAGESZ_4K, 0), 18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19 MAS3_SX|MAS3_SW|MAS3_SR, 0, 20 0, 0, BOOKE_PAGESZ_4K, 0), 21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22 MAS3_SX|MAS3_SW|MAS3_SR, 0, 23 0, 0, BOOKE_PAGESZ_4K, 0), 24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 26 0, 0, BOOKE_PAGESZ_4K, 0), 27 28 SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, 29 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 30 0, 0, BOOKE_PAGESZ_4K, 0), 31 32 /* TLB 1 */ 33 /* *I*G* - CCSRBAR */ 34 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 36 0, 0, BOOKE_PAGESZ_1M, 1), 37 38 /* W**G* - Flash/promjet, localbus */ 39 /* This will be changed to *I*G* after relocation to RAM. */ 40 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 41 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 42 0, 1, BOOKE_PAGESZ_256M, 1), 43 44 /* *I*G* - PCI */ 45 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, 46 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 47 0, 2, BOOKE_PAGESZ_1G, 1), 48 49 /* *I*G* - PCI I/O */ 50 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, 51 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 52 0, 3, BOOKE_PAGESZ_256K, 1), 53 54 /* *I*G - NAND */ 55 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 56 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57 0, 4, BOOKE_PAGESZ_1M, 1), 58 59 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 60 /* *I*G - L2SRAM */ 61 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 63 0, 5, BOOKE_PAGESZ_256K, 1), 64 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, 65 CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, 66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67 0, 6, BOOKE_PAGESZ_256K, 1), 68 #endif 69 }; 70 71 int num_tlb_entries = ARRAY_SIZE(tlb_table); 72