1 /* 2 * Copyright 2008 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/immap_fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <spd_sdram.h> 37 #include <fdt_support.h> 38 #include <tsec.h> 39 #include <netdev.h> 40 #include <sata.h> 41 42 #include "../common/pixis.h" 43 #include "../common/sgmii_riser.h" 44 45 phys_size_t fixed_sdram(void); 46 47 int board_early_init_f (void) 48 { 49 #ifdef CONFIG_MMC 50 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 51 52 setbits_be32(&gur->pmuxcr, 53 (MPC85xx_PMUXCR_SD_DATA | 54 MPC85xx_PMUXCR_SDHC_CD | 55 MPC85xx_PMUXCR_SDHC_WP)); 56 57 #endif 58 return 0; 59 } 60 61 int checkboard (void) 62 { 63 printf ("Board: MPC8536DS, System ID: 0x%02x, " 64 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 65 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 66 in8(PIXIS_BASE + PIXIS_PVER)); 67 return 0; 68 } 69 70 phys_size_t 71 initdram(int board_type) 72 { 73 phys_size_t dram_size = 0; 74 75 puts("Initializing...."); 76 77 #ifdef CONFIG_SPD_EEPROM 78 dram_size = fsl_ddr_sdram(); 79 #else 80 dram_size = fixed_sdram(); 81 #endif 82 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 83 dram_size *= 0x100000; 84 85 puts(" DDR: "); 86 return dram_size; 87 } 88 89 #if !defined(CONFIG_SPD_EEPROM) 90 /* 91 * Fixed sdram init -- doesn't use serial presence detect. 92 */ 93 94 phys_size_t fixed_sdram (void) 95 { 96 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 97 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 98 uint d_init; 99 100 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 101 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 102 103 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 104 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 105 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 106 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 107 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 108 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 109 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 110 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 111 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 112 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 113 114 #if defined (CONFIG_DDR_ECC) 115 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 116 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 117 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 118 #endif 119 asm("sync;isync"); 120 121 udelay(500); 122 123 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 124 125 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 126 d_init = 1; 127 debug("DDR - 1st controller: memory initializing\n"); 128 /* 129 * Poll until memory is initialized. 130 * 512 Meg at 400 might hit this 200 times or so. 131 */ 132 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 133 udelay(1000); 134 } 135 debug("DDR: memory initialized\n\n"); 136 asm("sync; isync"); 137 udelay(500); 138 #endif 139 140 return 512 * 1024 * 1024; 141 } 142 143 #endif 144 145 #ifdef CONFIG_PCI1 146 static struct pci_controller pci1_hose; 147 #endif 148 149 #ifdef CONFIG_PCIE1 150 static struct pci_controller pcie1_hose; 151 #endif 152 153 #ifdef CONFIG_PCIE2 154 static struct pci_controller pcie2_hose; 155 #endif 156 157 #ifdef CONFIG_PCIE3 158 static struct pci_controller pcie3_hose; 159 #endif 160 161 extern int fsl_pci_setup_inbound_windows(struct pci_region *r); 162 extern void fsl_pci_init(struct pci_controller *hose); 163 164 int first_free_busno=0; 165 166 void 167 pci_init_board(void) 168 { 169 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 170 uint devdisr = gur->devdisr; 171 uint sdrs2_io_sel = 172 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 173 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 174 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 175 176 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ 177 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); 178 179 if (sdrs2_io_sel == 7) 180 printf(" Serdes2 disalbed\n"); 181 else if (sdrs2_io_sel == 4) { 182 printf(" eTSEC1 is in sgmii mode.\n"); 183 printf(" eTSEC3 is in sgmii mode.\n"); 184 } else if (sdrs2_io_sel == 6) 185 printf(" eTSEC1 is in sgmii mode.\n"); 186 187 #ifdef CONFIG_PCIE3 188 { 189 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 190 struct pci_controller *hose = &pcie3_hose; 191 int pcie_ep = (host_agent == 1); 192 int pcie_configured = (io_sel == 7); 193 struct pci_region *r = hose->regions; 194 195 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 196 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", 197 pcie_ep ? "End Point" : "Root Complex", 198 (uint)pci); 199 if (pci->pme_msg_det) { 200 pci->pme_msg_det = 0xffffffff; 201 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 202 } 203 printf ("\n"); 204 205 /* inbound */ 206 r += fsl_pci_setup_inbound_windows(r); 207 208 /* outbound memory */ 209 pci_set_region(r++, 210 CONFIG_SYS_PCIE3_MEM_BUS, 211 CONFIG_SYS_PCIE3_MEM_PHYS, 212 CONFIG_SYS_PCIE3_MEM_SIZE, 213 PCI_REGION_MEM); 214 215 /* outbound io */ 216 pci_set_region(r++, 217 CONFIG_SYS_PCIE3_IO_BUS, 218 CONFIG_SYS_PCIE3_IO_PHYS, 219 CONFIG_SYS_PCIE3_IO_SIZE, 220 PCI_REGION_IO); 221 222 hose->region_count = r - hose->regions; 223 224 hose->first_busno=first_free_busno; 225 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 226 227 fsl_pci_init(hose); 228 229 first_free_busno=hose->last_busno+1; 230 printf (" PCIE3 on bus %02x - %02x\n", 231 hose->first_busno,hose->last_busno); 232 } else { 233 printf (" PCIE3: disabled\n"); 234 } 235 236 } 237 #else 238 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 239 #endif 240 241 #ifdef CONFIG_PCIE1 242 { 243 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 244 struct pci_controller *hose = &pcie1_hose; 245 int pcie_ep = (host_agent == 5); 246 int pcie_configured = (io_sel == 2 || io_sel == 3 247 || io_sel == 5 || io_sel == 7); 248 struct pci_region *r = hose->regions; 249 250 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 251 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", 252 pcie_ep ? "End Point" : "Root Complex", 253 (uint)pci); 254 if (pci->pme_msg_det) { 255 pci->pme_msg_det = 0xffffffff; 256 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 257 } 258 printf ("\n"); 259 260 /* inbound */ 261 r += fsl_pci_setup_inbound_windows(r); 262 263 /* outbound memory */ 264 pci_set_region(r++, 265 CONFIG_SYS_PCIE1_MEM_BUS, 266 CONFIG_SYS_PCIE1_MEM_PHYS, 267 CONFIG_SYS_PCIE1_MEM_SIZE, 268 PCI_REGION_MEM); 269 270 /* outbound io */ 271 pci_set_region(r++, 272 CONFIG_SYS_PCIE1_IO_BUS, 273 CONFIG_SYS_PCIE1_IO_PHYS, 274 CONFIG_SYS_PCIE1_IO_SIZE, 275 PCI_REGION_IO); 276 277 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 278 /* outbound memory */ 279 pci_set_region(r++, 280 CONFIG_SYS_PCIE1_MEM_BUS2, 281 CONFIG_SYS_PCIE1_MEM_PHYS2, 282 CONFIG_SYS_PCIE1_MEM_SIZE2, 283 PCI_REGION_MEM); 284 #endif 285 hose->region_count = r - hose->regions; 286 hose->first_busno=first_free_busno; 287 288 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 289 290 fsl_pci_init(hose); 291 292 first_free_busno=hose->last_busno+1; 293 printf(" PCIE1 on bus %02x - %02x\n", 294 hose->first_busno,hose->last_busno); 295 296 } else { 297 printf (" PCIE1: disabled\n"); 298 } 299 300 } 301 #else 302 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 303 #endif 304 305 #ifdef CONFIG_PCIE2 306 { 307 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 308 struct pci_controller *hose = &pcie2_hose; 309 int pcie_ep = (host_agent == 3); 310 int pcie_configured = (io_sel == 5 || io_sel == 7); 311 struct pci_region *r = hose->regions; 312 313 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 314 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", 315 pcie_ep ? "End Point" : "Root Complex", 316 (uint)pci); 317 if (pci->pme_msg_det) { 318 pci->pme_msg_det = 0xffffffff; 319 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 320 } 321 printf ("\n"); 322 323 /* inbound */ 324 r += fsl_pci_setup_inbound_windows(r); 325 326 /* outbound memory */ 327 pci_set_region(r++, 328 CONFIG_SYS_PCIE2_MEM_BUS, 329 CONFIG_SYS_PCIE2_MEM_PHYS, 330 CONFIG_SYS_PCIE2_MEM_SIZE, 331 PCI_REGION_MEM); 332 333 /* outbound io */ 334 pci_set_region(r++, 335 CONFIG_SYS_PCIE2_IO_BUS, 336 CONFIG_SYS_PCIE2_IO_PHYS, 337 CONFIG_SYS_PCIE2_IO_SIZE, 338 PCI_REGION_IO); 339 340 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 341 /* outbound memory */ 342 pci_set_region(r++, 343 CONFIG_SYS_PCIE2_MEM_BUS2, 344 CONFIG_SYS_PCIE2_MEM_PHYS2, 345 CONFIG_SYS_PCIE2_MEM_SIZE2, 346 PCI_REGION_MEM); 347 #endif 348 hose->region_count = r - hose->regions; 349 hose->first_busno=first_free_busno; 350 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 351 352 fsl_pci_init(hose); 353 first_free_busno=hose->last_busno+1; 354 printf (" PCIE2 on bus %02x - %02x\n", 355 hose->first_busno,hose->last_busno); 356 357 } else { 358 printf (" PCIE2: disabled\n"); 359 } 360 361 } 362 #else 363 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 364 #endif 365 366 367 #ifdef CONFIG_PCI1 368 { 369 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 370 struct pci_controller *hose = &pci1_hose; 371 struct pci_region *r = hose->regions; 372 373 uint pci_agent = (host_agent == 6); 374 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 375 uint pci_32 = 1; 376 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 377 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 378 379 380 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 381 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 382 (pci_32) ? 32 : 64, 383 (pci_speed == 33333000) ? "33" : 384 (pci_speed == 66666000) ? "66" : "unknown", 385 pci_clk_sel ? "sync" : "async", 386 pci_agent ? "agent" : "host", 387 pci_arb ? "arbiter" : "external-arbiter", 388 (uint)pci 389 ); 390 391 /* inbound */ 392 r += fsl_pci_setup_inbound_windows(r); 393 394 /* outbound memory */ 395 pci_set_region(r++, 396 CONFIG_SYS_PCI1_MEM_BUS, 397 CONFIG_SYS_PCI1_MEM_PHYS, 398 CONFIG_SYS_PCI1_MEM_SIZE, 399 PCI_REGION_MEM); 400 401 /* outbound io */ 402 pci_set_region(r++, 403 CONFIG_SYS_PCI1_IO_BUS, 404 CONFIG_SYS_PCI1_IO_PHYS, 405 CONFIG_SYS_PCI1_IO_SIZE, 406 PCI_REGION_IO); 407 408 #ifdef CONFIG_SYS_PCI1_MEM_BUS2 409 /* outbound memory */ 410 pci_set_region(r++, 411 CONFIG_SYS_PCI1_MEM_BUS2, 412 CONFIG_SYS_PCI1_MEM_PHYS2, 413 CONFIG_SYS_PCI1_MEM_SIZE2, 414 PCI_REGION_MEM); 415 #endif 416 hose->region_count = r - hose->regions; 417 hose->first_busno=first_free_busno; 418 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 419 420 fsl_pci_init(hose); 421 first_free_busno=hose->last_busno+1; 422 printf ("PCI on bus %02x - %02x\n", 423 hose->first_busno,hose->last_busno); 424 } else { 425 printf (" PCI: disabled\n"); 426 } 427 } 428 #else 429 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 430 #endif 431 } 432 433 434 int board_early_init_r(void) 435 { 436 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 437 const u8 flash_esel = 1; 438 439 /* 440 * Remap Boot flash + PROMJET region to caching-inhibited 441 * so that flash can be erased properly. 442 */ 443 444 /* Flush d-cache and invalidate i-cache of any FLASH data */ 445 flush_dcache(); 446 invalidate_icache(); 447 448 /* invalidate existing TLB entry for flash + promjet */ 449 disable_tlb(flash_esel); 450 451 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 452 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 453 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 454 455 return 0; 456 } 457 458 #ifdef CONFIG_GET_CLK_FROM_ICS307 459 /* decode S[0-2] to Output Divider (OD) */ 460 static unsigned char 461 ics307_S_to_OD[] = { 462 10, 2, 8, 4, 5, 7, 3, 6 463 }; 464 465 /* Calculate frequency being generated by ICS307-02 clock chip based upon 466 * the control bytes being programmed into it. */ 467 /* XXX: This function should probably go into a common library */ 468 static unsigned long 469 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 470 { 471 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 472 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 473 unsigned long RDW = cw2 & 0x7F; 474 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 475 unsigned long freq; 476 477 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 478 479 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 480 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 481 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 482 * 483 * R6:R0 = Reference Divider Word (RDW) 484 * V8:V0 = VCO Divider Word (VDW) 485 * S2:S0 = Output Divider Select (OD) 486 * F1:F0 = Function of CLK2 Output 487 * TTL = duty cycle 488 * C1:C0 = internal load capacitance for cyrstal 489 */ 490 491 /* Adding 1 to get a "nicely" rounded number, but this needs 492 * more tweaking to get a "properly" rounded number. */ 493 494 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 495 496 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 497 freq); 498 return freq; 499 } 500 501 unsigned long 502 get_board_sys_clk(ulong dummy) 503 { 504 return ics307_clk_freq ( 505 in8(PIXIS_BASE + PIXIS_VSYSCLK0), 506 in8(PIXIS_BASE + PIXIS_VSYSCLK1), 507 in8(PIXIS_BASE + PIXIS_VSYSCLK2) 508 ); 509 } 510 511 unsigned long 512 get_board_ddr_clk(ulong dummy) 513 { 514 return ics307_clk_freq ( 515 in8(PIXIS_BASE + PIXIS_VDDRCLK0), 516 in8(PIXIS_BASE + PIXIS_VDDRCLK1), 517 in8(PIXIS_BASE + PIXIS_VDDRCLK2) 518 ); 519 } 520 #else 521 unsigned long 522 get_board_sys_clk(ulong dummy) 523 { 524 u8 i; 525 ulong val = 0; 526 527 i = in8(PIXIS_BASE + PIXIS_SPD); 528 i &= 0x07; 529 530 switch (i) { 531 case 0: 532 val = 33333333; 533 break; 534 case 1: 535 val = 40000000; 536 break; 537 case 2: 538 val = 50000000; 539 break; 540 case 3: 541 val = 66666666; 542 break; 543 case 4: 544 val = 83333333; 545 break; 546 case 5: 547 val = 100000000; 548 break; 549 case 6: 550 val = 133333333; 551 break; 552 case 7: 553 val = 166666666; 554 break; 555 } 556 557 return val; 558 } 559 560 unsigned long 561 get_board_ddr_clk(ulong dummy) 562 { 563 u8 i; 564 ulong val = 0; 565 566 i = in8(PIXIS_BASE + PIXIS_SPD); 567 i &= 0x38; 568 i >>= 3; 569 570 switch (i) { 571 case 0: 572 val = 33333333; 573 break; 574 case 1: 575 val = 40000000; 576 break; 577 case 2: 578 val = 50000000; 579 break; 580 case 3: 581 val = 66666666; 582 break; 583 case 4: 584 val = 83333333; 585 break; 586 case 5: 587 val = 100000000; 588 break; 589 case 6: 590 val = 133333333; 591 break; 592 case 7: 593 val = 166666666; 594 break; 595 } 596 return val; 597 } 598 #endif 599 600 int sata_initialize(void) 601 { 602 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 603 uint sdrs2_io_sel = 604 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 605 if (sdrs2_io_sel & 0x04) 606 return 1; 607 608 return __sata_initialize(); 609 } 610 611 int board_eth_init(bd_t *bis) 612 { 613 #ifdef CONFIG_TSEC_ENET 614 struct tsec_info_struct tsec_info[2]; 615 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 616 int num = 0; 617 uint sdrs2_io_sel = 618 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 619 620 #ifdef CONFIG_TSEC1 621 SET_STD_TSEC_INFO(tsec_info[num], 1); 622 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { 623 tsec_info[num].phyaddr = 0; 624 tsec_info[num].flags |= TSEC_SGMII; 625 } 626 num++; 627 #endif 628 #ifdef CONFIG_TSEC3 629 SET_STD_TSEC_INFO(tsec_info[num], 3); 630 if (sdrs2_io_sel == 4) { 631 tsec_info[num].phyaddr = 1; 632 tsec_info[num].flags |= TSEC_SGMII; 633 } 634 num++; 635 #endif 636 637 if (!num) { 638 printf("No TSECs initialized\n"); 639 return 0; 640 } 641 642 #ifdef CONFIG_FSL_SGMII_RISER 643 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) 644 fsl_sgmii_riser_init(tsec_info, num); 645 #endif 646 647 tsec_eth_init(bis, tsec_info, num); 648 #endif 649 return pci_eth_init(bis); 650 } 651 652 #if defined(CONFIG_OF_BOARD_SETUP) 653 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, 654 struct pci_controller *hose); 655 656 void ft_board_setup(void *blob, bd_t *bd) 657 { 658 ft_cpu_setup(blob, bd); 659 660 #ifdef CONFIG_PCI1 661 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 662 #endif 663 #ifdef CONFIG_PCIE2 664 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 665 #endif 666 #ifdef CONFIG_PCIE2 667 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 668 #endif 669 #ifdef CONFIG_PCIE1 670 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); 671 #endif 672 #ifdef CONFIG_FSL_SGMII_RISER 673 fsl_sgmii_riser_fdt_fixup(blob); 674 #endif 675 } 676 #endif 677