1 /* 2 * Copyright 2008 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/immap_fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <spd_sdram.h> 37 #include <fdt_support.h> 38 #include <tsec.h> 39 #include <netdev.h> 40 41 #include "../common/pixis.h" 42 #include "../common/sgmii_riser.h" 43 44 phys_size_t fixed_sdram(void); 45 46 int checkboard (void) 47 { 48 printf ("Board: MPC8536DS, System ID: 0x%02x, " 49 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 50 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 51 in8(PIXIS_BASE + PIXIS_PVER)); 52 return 0; 53 } 54 55 phys_size_t 56 initdram(int board_type) 57 { 58 phys_size_t dram_size = 0; 59 60 puts("Initializing...."); 61 62 #ifdef CONFIG_SPD_EEPROM 63 dram_size = fsl_ddr_sdram(); 64 #else 65 dram_size = fixed_sdram(); 66 #endif 67 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 68 dram_size *= 0x100000; 69 70 puts(" DDR: "); 71 return dram_size; 72 } 73 74 #if !defined(CONFIG_SPD_EEPROM) 75 /* 76 * Fixed sdram init -- doesn't use serial presence detect. 77 */ 78 79 phys_size_t fixed_sdram (void) 80 { 81 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 82 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 83 uint d_init; 84 85 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 86 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 87 88 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 89 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 90 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 91 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 92 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 93 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 94 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 95 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 96 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 97 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 98 99 #if defined (CONFIG_DDR_ECC) 100 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 101 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 102 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 103 #endif 104 asm("sync;isync"); 105 106 udelay(500); 107 108 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 109 110 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 111 d_init = 1; 112 debug("DDR - 1st controller: memory initializing\n"); 113 /* 114 * Poll until memory is initialized. 115 * 512 Meg at 400 might hit this 200 times or so. 116 */ 117 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 118 udelay(1000); 119 } 120 debug("DDR: memory initialized\n\n"); 121 asm("sync; isync"); 122 udelay(500); 123 #endif 124 125 return 512 * 1024 * 1024; 126 } 127 128 #endif 129 130 #ifdef CONFIG_PCI1 131 static struct pci_controller pci1_hose; 132 #endif 133 134 #ifdef CONFIG_PCIE1 135 static struct pci_controller pcie1_hose; 136 #endif 137 138 #ifdef CONFIG_PCIE2 139 static struct pci_controller pcie2_hose; 140 #endif 141 142 #ifdef CONFIG_PCIE3 143 static struct pci_controller pcie3_hose; 144 #endif 145 146 extern int fsl_pci_setup_inbound_windows(struct pci_region *r); 147 extern void fsl_pci_init(struct pci_controller *hose); 148 149 int first_free_busno=0; 150 151 void 152 pci_init_board(void) 153 { 154 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 155 uint devdisr = gur->devdisr; 156 uint sdrs2_io_sel = 157 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 158 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 159 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 160 161 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ 162 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); 163 164 if (sdrs2_io_sel == 7) 165 printf(" Serdes2 disalbed\n"); 166 else if (sdrs2_io_sel == 4) { 167 printf(" eTSEC1 is in sgmii mode.\n"); 168 printf(" eTSEC3 is in sgmii mode.\n"); 169 } else if (sdrs2_io_sel == 6) 170 printf(" eTSEC1 is in sgmii mode.\n"); 171 172 #ifdef CONFIG_PCIE3 173 { 174 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 175 struct pci_controller *hose = &pcie3_hose; 176 int pcie_ep = (host_agent == 1); 177 int pcie_configured = (io_sel == 7); 178 struct pci_region *r = hose->regions; 179 180 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 181 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", 182 pcie_ep ? "End Point" : "Root Complex", 183 (uint)pci); 184 if (pci->pme_msg_det) { 185 pci->pme_msg_det = 0xffffffff; 186 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 187 } 188 printf ("\n"); 189 190 /* inbound */ 191 r += fsl_pci_setup_inbound_windows(r); 192 193 /* outbound memory */ 194 pci_set_region(r++, 195 CONFIG_SYS_PCIE3_MEM_BASE, 196 CONFIG_SYS_PCIE3_MEM_PHYS, 197 CONFIG_SYS_PCIE3_MEM_SIZE, 198 PCI_REGION_MEM); 199 200 /* outbound io */ 201 pci_set_region(r++, 202 CONFIG_SYS_PCIE3_IO_BASE, 203 CONFIG_SYS_PCIE3_IO_PHYS, 204 CONFIG_SYS_PCIE3_IO_SIZE, 205 PCI_REGION_IO); 206 207 hose->region_count = r - hose->regions; 208 209 hose->first_busno=first_free_busno; 210 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 211 212 fsl_pci_init(hose); 213 214 first_free_busno=hose->last_busno+1; 215 printf (" PCIE3 on bus %02x - %02x\n", 216 hose->first_busno,hose->last_busno); 217 } else { 218 printf (" PCIE3: disabled\n"); 219 } 220 221 } 222 #else 223 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 224 #endif 225 226 #ifdef CONFIG_PCIE1 227 { 228 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 229 struct pci_controller *hose = &pcie1_hose; 230 int pcie_ep = (host_agent == 5); 231 int pcie_configured = (io_sel == 2 || io_sel == 3 232 || io_sel == 5 || io_sel == 7); 233 struct pci_region *r = hose->regions; 234 235 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 236 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", 237 pcie_ep ? "End Point" : "Root Complex", 238 (uint)pci); 239 if (pci->pme_msg_det) { 240 pci->pme_msg_det = 0xffffffff; 241 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 242 } 243 printf ("\n"); 244 245 /* inbound */ 246 r += fsl_pci_setup_inbound_windows(r); 247 248 /* outbound memory */ 249 pci_set_region(r++, 250 CONFIG_SYS_PCIE1_MEM_BASE, 251 CONFIG_SYS_PCIE1_MEM_PHYS, 252 CONFIG_SYS_PCIE1_MEM_SIZE, 253 PCI_REGION_MEM); 254 255 /* outbound io */ 256 pci_set_region(r++, 257 CONFIG_SYS_PCIE1_IO_BASE, 258 CONFIG_SYS_PCIE1_IO_PHYS, 259 CONFIG_SYS_PCIE1_IO_SIZE, 260 PCI_REGION_IO); 261 262 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2 263 /* outbound memory */ 264 pci_set_region(r++, 265 CONFIG_SYS_PCIE1_MEM_BASE2, 266 CONFIG_SYS_PCIE1_MEM_PHYS2, 267 CONFIG_SYS_PCIE1_MEM_SIZE2, 268 PCI_REGION_MEM); 269 #endif 270 hose->region_count = r - hose->regions; 271 hose->first_busno=first_free_busno; 272 273 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 274 275 fsl_pci_init(hose); 276 277 first_free_busno=hose->last_busno+1; 278 printf(" PCIE1 on bus %02x - %02x\n", 279 hose->first_busno,hose->last_busno); 280 281 } else { 282 printf (" PCIE1: disabled\n"); 283 } 284 285 } 286 #else 287 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 288 #endif 289 290 #ifdef CONFIG_PCIE2 291 { 292 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 293 struct pci_controller *hose = &pcie2_hose; 294 int pcie_ep = (host_agent == 3); 295 int pcie_configured = (io_sel == 5 || io_sel == 7); 296 struct pci_region *r = hose->regions; 297 298 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 299 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", 300 pcie_ep ? "End Point" : "Root Complex", 301 (uint)pci); 302 if (pci->pme_msg_det) { 303 pci->pme_msg_det = 0xffffffff; 304 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 305 } 306 printf ("\n"); 307 308 /* inbound */ 309 r += fsl_pci_setup_inbound_windows(r); 310 311 /* outbound memory */ 312 pci_set_region(r++, 313 CONFIG_SYS_PCIE2_MEM_BASE, 314 CONFIG_SYS_PCIE2_MEM_PHYS, 315 CONFIG_SYS_PCIE2_MEM_SIZE, 316 PCI_REGION_MEM); 317 318 /* outbound io */ 319 pci_set_region(r++, 320 CONFIG_SYS_PCIE2_IO_BASE, 321 CONFIG_SYS_PCIE2_IO_PHYS, 322 CONFIG_SYS_PCIE2_IO_SIZE, 323 PCI_REGION_IO); 324 325 #ifdef CONFIG_SYS_PCIE2_MEM_BASE2 326 /* outbound memory */ 327 pci_set_region(r++, 328 CONFIG_SYS_PCIE2_MEM_BASE2, 329 CONFIG_SYS_PCIE2_MEM_PHYS2, 330 CONFIG_SYS_PCIE2_MEM_SIZE2, 331 PCI_REGION_MEM); 332 #endif 333 hose->region_count = r - hose->regions; 334 hose->first_busno=first_free_busno; 335 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 336 337 fsl_pci_init(hose); 338 first_free_busno=hose->last_busno+1; 339 printf (" PCIE2 on bus %02x - %02x\n", 340 hose->first_busno,hose->last_busno); 341 342 } else { 343 printf (" PCIE2: disabled\n"); 344 } 345 346 } 347 #else 348 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 349 #endif 350 351 352 #ifdef CONFIG_PCI1 353 { 354 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 355 struct pci_controller *hose = &pci1_hose; 356 struct pci_region *r = hose->regions; 357 358 uint pci_agent = (host_agent == 6); 359 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 360 uint pci_32 = 1; 361 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 362 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 363 364 365 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 366 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 367 (pci_32) ? 32 : 64, 368 (pci_speed == 33333000) ? "33" : 369 (pci_speed == 66666000) ? "66" : "unknown", 370 pci_clk_sel ? "sync" : "async", 371 pci_agent ? "agent" : "host", 372 pci_arb ? "arbiter" : "external-arbiter", 373 (uint)pci 374 ); 375 376 /* inbound */ 377 r += fsl_pci_setup_inbound_windows(r); 378 379 /* outbound memory */ 380 pci_set_region(r++, 381 CONFIG_SYS_PCI1_MEM_BASE, 382 CONFIG_SYS_PCI1_MEM_PHYS, 383 CONFIG_SYS_PCI1_MEM_SIZE, 384 PCI_REGION_MEM); 385 386 /* outbound io */ 387 pci_set_region(r++, 388 CONFIG_SYS_PCI1_IO_BASE, 389 CONFIG_SYS_PCI1_IO_PHYS, 390 CONFIG_SYS_PCI1_IO_SIZE, 391 PCI_REGION_IO); 392 393 #ifdef CONFIG_SYS_PCI1_MEM_BASE2 394 /* outbound memory */ 395 pci_set_region(r++, 396 CONFIG_SYS_PCI1_MEM_BASE2, 397 CONFIG_SYS_PCI1_MEM_PHYS2, 398 CONFIG_SYS_PCI1_MEM_SIZE2, 399 PCI_REGION_MEM); 400 #endif 401 hose->region_count = r - hose->regions; 402 hose->first_busno=first_free_busno; 403 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 404 405 fsl_pci_init(hose); 406 first_free_busno=hose->last_busno+1; 407 printf ("PCI on bus %02x - %02x\n", 408 hose->first_busno,hose->last_busno); 409 } else { 410 printf (" PCI: disabled\n"); 411 } 412 } 413 #else 414 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 415 #endif 416 } 417 418 419 int board_early_init_r(void) 420 { 421 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 422 const u8 flash_esel = 1; 423 424 /* 425 * Remap Boot flash + PROMJET region to caching-inhibited 426 * so that flash can be erased properly. 427 */ 428 429 /* Flush d-cache and invalidate i-cache of any FLASH data */ 430 flush_dcache(); 431 invalidate_icache(); 432 433 /* invalidate existing TLB entry for flash + promjet */ 434 disable_tlb(flash_esel); 435 436 set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ 437 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 438 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 439 440 return 0; 441 } 442 443 #ifdef CONFIG_GET_CLK_FROM_ICS307 444 /* decode S[0-2] to Output Divider (OD) */ 445 static unsigned char 446 ics307_S_to_OD[] = { 447 10, 2, 8, 4, 5, 7, 3, 6 448 }; 449 450 /* Calculate frequency being generated by ICS307-02 clock chip based upon 451 * the control bytes being programmed into it. */ 452 /* XXX: This function should probably go into a common library */ 453 static unsigned long 454 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 455 { 456 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 457 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 458 unsigned long RDW = cw2 & 0x7F; 459 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 460 unsigned long freq; 461 462 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 463 464 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 465 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 466 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 467 * 468 * R6:R0 = Reference Divider Word (RDW) 469 * V8:V0 = VCO Divider Word (VDW) 470 * S2:S0 = Output Divider Select (OD) 471 * F1:F0 = Function of CLK2 Output 472 * TTL = duty cycle 473 * C1:C0 = internal load capacitance for cyrstal 474 */ 475 476 /* Adding 1 to get a "nicely" rounded number, but this needs 477 * more tweaking to get a "properly" rounded number. */ 478 479 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 480 481 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 482 freq); 483 return freq; 484 } 485 486 unsigned long 487 get_board_sys_clk(ulong dummy) 488 { 489 return ics307_clk_freq ( 490 in8(PIXIS_BASE + PIXIS_VSYSCLK0), 491 in8(PIXIS_BASE + PIXIS_VSYSCLK1), 492 in8(PIXIS_BASE + PIXIS_VSYSCLK2) 493 ); 494 } 495 496 unsigned long 497 get_board_ddr_clk(ulong dummy) 498 { 499 return ics307_clk_freq ( 500 in8(PIXIS_BASE + PIXIS_VDDRCLK0), 501 in8(PIXIS_BASE + PIXIS_VDDRCLK1), 502 in8(PIXIS_BASE + PIXIS_VDDRCLK2) 503 ); 504 } 505 #else 506 unsigned long 507 get_board_sys_clk(ulong dummy) 508 { 509 u8 i; 510 ulong val = 0; 511 512 i = in8(PIXIS_BASE + PIXIS_SPD); 513 i &= 0x07; 514 515 switch (i) { 516 case 0: 517 val = 33333333; 518 break; 519 case 1: 520 val = 40000000; 521 break; 522 case 2: 523 val = 50000000; 524 break; 525 case 3: 526 val = 66666666; 527 break; 528 case 4: 529 val = 83333333; 530 break; 531 case 5: 532 val = 100000000; 533 break; 534 case 6: 535 val = 133333333; 536 break; 537 case 7: 538 val = 166666666; 539 break; 540 } 541 542 return val; 543 } 544 545 unsigned long 546 get_board_ddr_clk(ulong dummy) 547 { 548 u8 i; 549 ulong val = 0; 550 551 i = in8(PIXIS_BASE + PIXIS_SPD); 552 i &= 0x38; 553 i >>= 3; 554 555 switch (i) { 556 case 0: 557 val = 33333333; 558 break; 559 case 1: 560 val = 40000000; 561 break; 562 case 2: 563 val = 50000000; 564 break; 565 case 3: 566 val = 66666666; 567 break; 568 case 4: 569 val = 83333333; 570 break; 571 case 5: 572 val = 100000000; 573 break; 574 case 6: 575 val = 133333333; 576 break; 577 case 7: 578 val = 166666666; 579 break; 580 } 581 return val; 582 } 583 #endif 584 585 int is_sata_supported(void) 586 { 587 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 588 uint sdrs2_io_sel = 589 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 590 if (sdrs2_io_sel & 0x04) 591 return 0; 592 593 return 1; 594 } 595 596 int board_eth_init(bd_t *bis) 597 { 598 #ifdef CONFIG_TSEC_ENET 599 struct tsec_info_struct tsec_info[2]; 600 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 601 int num = 0; 602 uint sdrs2_io_sel = 603 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 604 605 #ifdef CONFIG_TSEC1 606 SET_STD_TSEC_INFO(tsec_info[num], 1); 607 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { 608 tsec_info[num].phyaddr = 0; 609 tsec_info[num].flags |= TSEC_SGMII; 610 } 611 num++; 612 #endif 613 #ifdef CONFIG_TSEC3 614 SET_STD_TSEC_INFO(tsec_info[num], 3); 615 if (sdrs2_io_sel == 4) { 616 tsec_info[num].phyaddr = 1; 617 tsec_info[num].flags |= TSEC_SGMII; 618 } 619 num++; 620 #endif 621 622 if (!num) { 623 printf("No TSECs initialized\n"); 624 return 0; 625 } 626 627 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) 628 fsl_sgmii_riser_init(tsec_info, num); 629 630 tsec_eth_init(bis, tsec_info, num); 631 #endif 632 return pci_eth_init(bis); 633 } 634 635 #if defined(CONFIG_OF_BOARD_SETUP) 636 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, 637 struct pci_controller *hose); 638 639 void ft_board_setup(void *blob, bd_t *bd) 640 { 641 ft_cpu_setup(blob, bd); 642 643 #ifdef CONFIG_PCI1 644 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 645 #endif 646 #ifdef CONFIG_PCIE2 647 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 648 #endif 649 #ifdef CONFIG_PCIE2 650 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 651 #endif 652 #ifdef CONFIG_PCIE1 653 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); 654 #endif 655 } 656 #endif 657