1 /* 2 * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <asm/fsl_serdes.h> 34 #include <spd.h> 35 #include <miiphy.h> 36 #include <libfdt.h> 37 #include <spd_sdram.h> 38 #include <fdt_support.h> 39 #include <fsl_mdio.h> 40 #include <tsec.h> 41 #include <netdev.h> 42 #include <sata.h> 43 44 #include "../common/sgmii_riser.h" 45 46 int board_early_init_f (void) 47 { 48 #ifdef CONFIG_MMC 49 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50 51 setbits_be32(&gur->pmuxcr, 52 (MPC85xx_PMUXCR_SDHC_CD | 53 MPC85xx_PMUXCR_SDHC_WP)); 54 55 /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118, 56 * however, this erratum only applies to MPC8536 Rev1.0. 57 * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/ 58 if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) && 59 (SVR_MIN(get_svr()) >= 0x1)) 60 || (SVR_MAJ(get_svr() & 0x7) > 0x1)) 61 setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV); 62 #endif 63 return 0; 64 } 65 66 int checkboard (void) 67 { 68 u8 vboot; 69 u8 *pixis_base = (u8 *)PIXIS_BASE; 70 71 puts("Board: MPC8536DS "); 72 #ifdef CONFIG_PHYS_64BIT 73 puts("(36-bit addrmap) "); 74 #endif 75 76 printf ("Sys ID: 0x%02x, " 77 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 78 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 79 in_8(pixis_base + PIXIS_PVER)); 80 81 vboot = in_8(pixis_base + PIXIS_VBOOT); 82 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 83 case PIXIS_VBOOT_LBMAP_NOR0: 84 puts ("vBank: 0\n"); 85 break; 86 case PIXIS_VBOOT_LBMAP_NOR1: 87 puts ("vBank: 1\n"); 88 break; 89 case PIXIS_VBOOT_LBMAP_NOR2: 90 puts ("vBank: 2\n"); 91 break; 92 case PIXIS_VBOOT_LBMAP_NOR3: 93 puts ("vBank: 3\n"); 94 break; 95 case PIXIS_VBOOT_LBMAP_PJET: 96 puts ("Promjet\n"); 97 break; 98 case PIXIS_VBOOT_LBMAP_NAND: 99 puts ("NAND\n"); 100 break; 101 } 102 103 return 0; 104 } 105 106 #if !defined(CONFIG_SPD_EEPROM) 107 /* 108 * Fixed sdram init -- doesn't use serial presence detect. 109 */ 110 111 phys_size_t fixed_sdram (void) 112 { 113 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 114 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 115 uint d_init; 116 117 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 118 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 119 120 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 121 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 122 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 123 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 124 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 125 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 126 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 127 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 128 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 129 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 130 131 #if defined (CONFIG_DDR_ECC) 132 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 133 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 134 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 135 #endif 136 asm("sync;isync"); 137 138 udelay(500); 139 140 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 141 142 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 143 d_init = 1; 144 debug("DDR - 1st controller: memory initializing\n"); 145 /* 146 * Poll until memory is initialized. 147 * 512 Meg at 400 might hit this 200 times or so. 148 */ 149 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 150 udelay(1000); 151 } 152 debug("DDR: memory initialized\n\n"); 153 asm("sync; isync"); 154 udelay(500); 155 #endif 156 157 return 512 * 1024 * 1024; 158 } 159 160 #endif 161 162 #ifdef CONFIG_PCI1 163 static struct pci_controller pci1_hose; 164 #endif 165 166 #ifdef CONFIG_PCI 167 void pci_init_board(void) 168 { 169 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 170 struct fsl_pci_info pci_info; 171 u32 devdisr, pordevsr; 172 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 173 int first_free_busno; 174 175 first_free_busno = fsl_pcie_init_board(0); 176 177 #ifdef CONFIG_PCI1 178 devdisr = in_be32(&gur->devdisr); 179 pordevsr = in_be32(&gur->pordevsr); 180 porpllsr = in_be32(&gur->porpllsr); 181 182 pci_speed = 66666000; 183 pci_32 = 1; 184 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 185 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 186 187 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 188 SET_STD_PCI_INFO(pci_info, 1); 189 set_next_law(pci_info.mem_phys, 190 law_size_bits(pci_info.mem_size), pci_info.law); 191 set_next_law(pci_info.io_phys, 192 law_size_bits(pci_info.io_size), pci_info.law); 193 194 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 195 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 196 (pci_32) ? 32 : 64, 197 (pci_speed == 33333000) ? "33" : 198 (pci_speed == 66666000) ? "66" : "unknown", 199 pci_clk_sel ? "sync" : "async", 200 pci_agent ? "agent" : "host", 201 pci_arb ? "arbiter" : "external-arbiter", 202 pci_info.regs); 203 204 first_free_busno = fsl_pci_init_port(&pci_info, 205 &pci1_hose, first_free_busno); 206 } else { 207 printf("PCI: disabled\n"); 208 } 209 210 puts("\n"); 211 #else 212 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 213 #endif 214 } 215 #endif 216 217 int board_early_init_r(void) 218 { 219 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 220 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 221 222 /* 223 * Remap Boot flash + PROMJET region to caching-inhibited 224 * so that flash can be erased properly. 225 */ 226 227 /* Flush d-cache and invalidate i-cache of any FLASH data */ 228 flush_dcache(); 229 invalidate_icache(); 230 231 /* invalidate existing TLB entry for flash + promjet */ 232 disable_tlb(flash_esel); 233 234 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 235 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 236 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 237 238 return 0; 239 } 240 241 int board_eth_init(bd_t *bis) 242 { 243 #ifdef CONFIG_TSEC_ENET 244 struct fsl_pq_mdio_info mdio_info; 245 struct tsec_info_struct tsec_info[2]; 246 int num = 0; 247 248 #ifdef CONFIG_TSEC1 249 SET_STD_TSEC_INFO(tsec_info[num], 1); 250 if (is_serdes_configured(SGMII_TSEC1)) { 251 puts("eTSEC1 is in sgmii mode.\n"); 252 tsec_info[num].phyaddr = 0; 253 tsec_info[num].flags |= TSEC_SGMII; 254 } 255 num++; 256 #endif 257 #ifdef CONFIG_TSEC3 258 SET_STD_TSEC_INFO(tsec_info[num], 3); 259 if (is_serdes_configured(SGMII_TSEC3)) { 260 puts("eTSEC3 is in sgmii mode.\n"); 261 tsec_info[num].phyaddr = 1; 262 tsec_info[num].flags |= TSEC_SGMII; 263 } 264 num++; 265 #endif 266 267 if (!num) { 268 printf("No TSECs initialized\n"); 269 return 0; 270 } 271 272 #ifdef CONFIG_FSL_SGMII_RISER 273 if (is_serdes_configured(SGMII_TSEC1) || 274 is_serdes_configured(SGMII_TSEC3)) { 275 fsl_sgmii_riser_init(tsec_info, num); 276 } 277 #endif 278 279 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 280 mdio_info.name = DEFAULT_MII_NAME; 281 fsl_pq_mdio_init(bis, &mdio_info); 282 283 tsec_eth_init(bis, tsec_info, num); 284 #endif 285 return pci_eth_init(bis); 286 } 287 288 #if defined(CONFIG_OF_BOARD_SETUP) 289 void ft_board_setup(void *blob, bd_t *bd) 290 { 291 ft_cpu_setup(blob, bd); 292 293 FT_FSL_PCI_SETUP; 294 295 #ifdef CONFIG_FSL_SGMII_RISER 296 fsl_sgmii_riser_fdt_fixup(blob); 297 #endif 298 } 299 #endif 300