1 /* 2 * Copyright 2008-2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <spd_sdram.h> 37 #include <fdt_support.h> 38 #include <tsec.h> 39 #include <netdev.h> 40 #include <sata.h> 41 42 #include "../common/sgmii_riser.h" 43 44 phys_size_t fixed_sdram(void); 45 46 int board_early_init_f (void) 47 { 48 #ifdef CONFIG_MMC 49 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50 51 setbits_be32(&gur->pmuxcr, 52 (MPC85xx_PMUXCR_SD_DATA | 53 MPC85xx_PMUXCR_SDHC_CD | 54 MPC85xx_PMUXCR_SDHC_WP)); 55 56 #endif 57 return 0; 58 } 59 60 int checkboard (void) 61 { 62 u8 vboot; 63 u8 *pixis_base = (u8 *)PIXIS_BASE; 64 65 puts("Board: MPC8536DS "); 66 #ifdef CONFIG_PHYS_64BIT 67 puts("(36-bit addrmap) "); 68 #endif 69 70 printf ("Sys ID: 0x%02x, " 71 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 72 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 73 in_8(pixis_base + PIXIS_PVER)); 74 75 vboot = in_8(pixis_base + PIXIS_VBOOT); 76 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 77 case PIXIS_VBOOT_LBMAP_NOR0: 78 puts ("vBank: 0\n"); 79 break; 80 case PIXIS_VBOOT_LBMAP_NOR1: 81 puts ("vBank: 1\n"); 82 break; 83 case PIXIS_VBOOT_LBMAP_NOR2: 84 puts ("vBank: 2\n"); 85 break; 86 case PIXIS_VBOOT_LBMAP_NOR3: 87 puts ("vBank: 3\n"); 88 break; 89 case PIXIS_VBOOT_LBMAP_PJET: 90 puts ("Promjet\n"); 91 break; 92 case PIXIS_VBOOT_LBMAP_NAND: 93 puts ("NAND\n"); 94 break; 95 } 96 97 return 0; 98 } 99 100 phys_size_t 101 initdram(int board_type) 102 { 103 phys_size_t dram_size = 0; 104 105 puts("Initializing...."); 106 107 #ifdef CONFIG_SPD_EEPROM 108 dram_size = fsl_ddr_sdram(); 109 #else 110 dram_size = fixed_sdram(); 111 #endif 112 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 113 dram_size *= 0x100000; 114 115 puts(" DDR: "); 116 return dram_size; 117 } 118 119 #if !defined(CONFIG_SPD_EEPROM) 120 /* 121 * Fixed sdram init -- doesn't use serial presence detect. 122 */ 123 124 phys_size_t fixed_sdram (void) 125 { 126 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 127 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 128 uint d_init; 129 130 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 131 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 132 133 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 134 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 135 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 136 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 137 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 138 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 139 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 140 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 141 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 142 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 143 144 #if defined (CONFIG_DDR_ECC) 145 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 146 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 147 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 148 #endif 149 asm("sync;isync"); 150 151 udelay(500); 152 153 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 154 155 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 156 d_init = 1; 157 debug("DDR - 1st controller: memory initializing\n"); 158 /* 159 * Poll until memory is initialized. 160 * 512 Meg at 400 might hit this 200 times or so. 161 */ 162 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 163 udelay(1000); 164 } 165 debug("DDR: memory initialized\n\n"); 166 asm("sync; isync"); 167 udelay(500); 168 #endif 169 170 return 512 * 1024 * 1024; 171 } 172 173 #endif 174 175 #ifdef CONFIG_PCI1 176 static struct pci_controller pci1_hose; 177 #endif 178 179 #ifdef CONFIG_PCIE1 180 static struct pci_controller pcie1_hose; 181 #endif 182 183 #ifdef CONFIG_PCIE2 184 static struct pci_controller pcie2_hose; 185 #endif 186 187 #ifdef CONFIG_PCIE3 188 static struct pci_controller pcie3_hose; 189 #endif 190 191 #ifdef CONFIG_PCI 192 void pci_init_board(void) 193 { 194 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 195 struct fsl_pci_info pci_info[4]; 196 u32 devdisr, pordevsr, io_sel, sdrs2_io_sel; 197 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 198 int first_free_busno = 0; 199 int num = 0; 200 201 int pcie_ep, pcie_configured; 202 203 devdisr = in_be32(&gur->devdisr); 204 pordevsr = in_be32(&gur->pordevsr); 205 porpllsr = in_be32(&gur->porpllsr); 206 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 207 sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 208 209 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n", 210 devdisr, sdrs2_io_sel, io_sel); 211 212 if (sdrs2_io_sel == 7) 213 printf(" Serdes2 disalbed\n"); 214 else if (sdrs2_io_sel == 4) { 215 printf(" eTSEC1 is in sgmii mode.\n"); 216 printf(" eTSEC3 is in sgmii mode.\n"); 217 } else if (sdrs2_io_sel == 6) 218 printf(" eTSEC1 is in sgmii mode.\n"); 219 220 puts("\n"); 221 #ifdef CONFIG_PCIE3 222 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); 223 224 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 225 SET_STD_PCIE_INFO(pci_info[num], 3); 226 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); 227 printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n", 228 pcie_ep ? "Endpoint" : "Root Complex", 229 pci_info[num].regs); 230 first_free_busno = fsl_pci_init_port(&pci_info[num++], 231 &pcie3_hose, first_free_busno); 232 } else { 233 printf (" PCIE3: disabled\n"); 234 } 235 236 puts("\n"); 237 #else 238 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 239 #endif 240 241 #ifdef CONFIG_PCIE1 242 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 243 244 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 245 SET_STD_PCIE_INFO(pci_info[num], 1); 246 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 247 printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n", 248 pcie_ep ? "Endpoint" : "Root Complex", 249 pci_info[num].regs); 250 first_free_busno = fsl_pci_init_port(&pci_info[num++], 251 &pcie1_hose, first_free_busno); 252 } else { 253 printf (" PCIE1: disabled\n"); 254 } 255 256 puts("\n"); 257 #else 258 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 259 #endif 260 261 #ifdef CONFIG_PCIE2 262 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 263 264 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ 265 SET_STD_PCIE_INFO(pci_info[num], 2); 266 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 267 printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n", 268 pcie_ep ? "Endpoint" : "Root Complex", 269 pci_info[num].regs); 270 first_free_busno = fsl_pci_init_port(&pci_info[num++], 271 &pcie2_hose, first_free_busno); 272 } else { 273 printf (" PCIE2: disabled\n"); 274 } 275 276 puts("\n"); 277 #else 278 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 279 #endif 280 281 #ifdef CONFIG_PCI1 282 pci_speed = 66666000; 283 pci_32 = 1; 284 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 285 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 286 287 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 288 SET_STD_PCI_INFO(pci_info[num], 1); 289 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 290 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 291 (pci_32) ? 32 : 64, 292 (pci_speed == 33333000) ? "33" : 293 (pci_speed == 66666000) ? "66" : "unknown", 294 pci_clk_sel ? "sync" : "async", 295 pci_agent ? "agent" : "host", 296 pci_arb ? "arbiter" : "external-arbiter", 297 pci_info[num].regs); 298 299 first_free_busno = fsl_pci_init_port(&pci_info[num++], 300 &pci1_hose, first_free_busno); 301 } else { 302 printf (" PCI: disabled\n"); 303 } 304 305 puts("\n"); 306 #else 307 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 308 #endif 309 } 310 #endif 311 312 int board_early_init_r(void) 313 { 314 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 315 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 316 317 /* 318 * Remap Boot flash + PROMJET region to caching-inhibited 319 * so that flash can be erased properly. 320 */ 321 322 /* Flush d-cache and invalidate i-cache of any FLASH data */ 323 flush_dcache(); 324 invalidate_icache(); 325 326 /* invalidate existing TLB entry for flash + promjet */ 327 disable_tlb(flash_esel); 328 329 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 330 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 331 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 332 333 return 0; 334 } 335 336 #ifdef CONFIG_GET_CLK_FROM_ICS307 337 /* decode S[0-2] to Output Divider (OD) */ 338 static unsigned char 339 ics307_S_to_OD[] = { 340 10, 2, 8, 4, 5, 7, 3, 6 341 }; 342 343 /* Calculate frequency being generated by ICS307-02 clock chip based upon 344 * the control bytes being programmed into it. */ 345 /* XXX: This function should probably go into a common library */ 346 static unsigned long 347 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 348 { 349 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 350 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 351 unsigned long RDW = cw2 & 0x7F; 352 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 353 unsigned long freq; 354 355 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 356 357 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 358 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 359 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 360 * 361 * R6:R0 = Reference Divider Word (RDW) 362 * V8:V0 = VCO Divider Word (VDW) 363 * S2:S0 = Output Divider Select (OD) 364 * F1:F0 = Function of CLK2 Output 365 * TTL = duty cycle 366 * C1:C0 = internal load capacitance for cyrstal 367 */ 368 369 /* Adding 1 to get a "nicely" rounded number, but this needs 370 * more tweaking to get a "properly" rounded number. */ 371 372 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 373 374 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 375 freq); 376 return freq; 377 } 378 379 unsigned long 380 get_board_sys_clk(ulong dummy) 381 { 382 u8 *pixis_base = (u8 *)PIXIS_BASE; 383 384 return ics307_clk_freq ( 385 in_8(pixis_base + PIXIS_VSYSCLK0), 386 in_8(pixis_base + PIXIS_VSYSCLK1), 387 in_8(pixis_base + PIXIS_VSYSCLK2) 388 ); 389 } 390 391 unsigned long 392 get_board_ddr_clk(ulong dummy) 393 { 394 u8 *pixis_base = (u8 *)PIXIS_BASE; 395 396 return ics307_clk_freq ( 397 in_8(pixis_base + PIXIS_VDDRCLK0), 398 in_8(pixis_base + PIXIS_VDDRCLK1), 399 in_8(pixis_base + PIXIS_VDDRCLK2) 400 ); 401 } 402 #else 403 unsigned long 404 get_board_sys_clk(ulong dummy) 405 { 406 u8 i; 407 ulong val = 0; 408 u8 *pixis_base = (u8 *)PIXIS_BASE; 409 410 i = in_8(pixis_base + PIXIS_SPD); 411 i &= 0x07; 412 413 switch (i) { 414 case 0: 415 val = 33333333; 416 break; 417 case 1: 418 val = 40000000; 419 break; 420 case 2: 421 val = 50000000; 422 break; 423 case 3: 424 val = 66666666; 425 break; 426 case 4: 427 val = 83333333; 428 break; 429 case 5: 430 val = 100000000; 431 break; 432 case 6: 433 val = 133333333; 434 break; 435 case 7: 436 val = 166666666; 437 break; 438 } 439 440 return val; 441 } 442 443 unsigned long 444 get_board_ddr_clk(ulong dummy) 445 { 446 u8 i; 447 ulong val = 0; 448 u8 *pixis_base = (u8 *)PIXIS_BASE; 449 450 i = in_8(pixis_base + PIXIS_SPD); 451 i &= 0x38; 452 i >>= 3; 453 454 switch (i) { 455 case 0: 456 val = 33333333; 457 break; 458 case 1: 459 val = 40000000; 460 break; 461 case 2: 462 val = 50000000; 463 break; 464 case 3: 465 val = 66666666; 466 break; 467 case 4: 468 val = 83333333; 469 break; 470 case 5: 471 val = 100000000; 472 break; 473 case 6: 474 val = 133333333; 475 break; 476 case 7: 477 val = 166666666; 478 break; 479 } 480 return val; 481 } 482 #endif 483 484 int sata_initialize(void) 485 { 486 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 487 uint sdrs2_io_sel = 488 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 489 if (sdrs2_io_sel & 0x04) 490 return 1; 491 492 return __sata_initialize(); 493 } 494 495 int board_eth_init(bd_t *bis) 496 { 497 #ifdef CONFIG_TSEC_ENET 498 struct tsec_info_struct tsec_info[2]; 499 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 500 int num = 0; 501 uint sdrs2_io_sel = 502 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 503 504 #ifdef CONFIG_TSEC1 505 SET_STD_TSEC_INFO(tsec_info[num], 1); 506 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { 507 tsec_info[num].phyaddr = 0; 508 tsec_info[num].flags |= TSEC_SGMII; 509 } 510 num++; 511 #endif 512 #ifdef CONFIG_TSEC3 513 SET_STD_TSEC_INFO(tsec_info[num], 3); 514 if (sdrs2_io_sel == 4) { 515 tsec_info[num].phyaddr = 1; 516 tsec_info[num].flags |= TSEC_SGMII; 517 } 518 num++; 519 #endif 520 521 if (!num) { 522 printf("No TSECs initialized\n"); 523 return 0; 524 } 525 526 #ifdef CONFIG_FSL_SGMII_RISER 527 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) 528 fsl_sgmii_riser_init(tsec_info, num); 529 #endif 530 531 tsec_eth_init(bis, tsec_info, num); 532 #endif 533 return pci_eth_init(bis); 534 } 535 536 #if defined(CONFIG_OF_BOARD_SETUP) 537 void ft_board_setup(void *blob, bd_t *bd) 538 { 539 ft_cpu_setup(blob, bd); 540 541 #ifdef CONFIG_PCI1 542 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 543 #endif 544 #ifdef CONFIG_PCIE2 545 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 546 #endif 547 #ifdef CONFIG_PCIE2 548 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 549 #endif 550 #ifdef CONFIG_PCIE1 551 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); 552 #endif 553 #ifdef CONFIG_FSL_SGMII_RISER 554 fsl_sgmii_riser_fdt_fixup(blob); 555 #endif 556 } 557 #endif 558