1 /* 2 * Copyright 2008-2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <spd_sdram.h> 37 #include <fdt_support.h> 38 #include <tsec.h> 39 #include <netdev.h> 40 #include <sata.h> 41 42 #include "../common/pixis.h" 43 #include "../common/sgmii_riser.h" 44 45 phys_size_t fixed_sdram(void); 46 47 int board_early_init_f (void) 48 { 49 #ifdef CONFIG_MMC 50 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 51 52 setbits_be32(&gur->pmuxcr, 53 (MPC85xx_PMUXCR_SD_DATA | 54 MPC85xx_PMUXCR_SDHC_CD | 55 MPC85xx_PMUXCR_SDHC_WP)); 56 57 #endif 58 return 0; 59 } 60 61 int checkboard (void) 62 { 63 u8 vboot; 64 u8 *pixis_base = (u8 *)PIXIS_BASE; 65 66 puts("Board: MPC8536DS "); 67 #ifdef CONFIG_PHYS_64BIT 68 puts("(36-bit addrmap) "); 69 #endif 70 71 printf ("Sys ID: 0x%02x, " 72 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 73 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 74 in_8(pixis_base + PIXIS_PVER)); 75 76 vboot = in_8(pixis_base + PIXIS_VBOOT); 77 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 78 case PIXIS_VBOOT_LBMAP_NOR0: 79 puts ("vBank: 0\n"); 80 break; 81 case PIXIS_VBOOT_LBMAP_NOR1: 82 puts ("vBank: 1\n"); 83 break; 84 case PIXIS_VBOOT_LBMAP_NOR2: 85 puts ("vBank: 2\n"); 86 break; 87 case PIXIS_VBOOT_LBMAP_NOR3: 88 puts ("vBank: 3\n"); 89 break; 90 case PIXIS_VBOOT_LBMAP_PJET: 91 puts ("Promjet\n"); 92 break; 93 case PIXIS_VBOOT_LBMAP_NAND: 94 puts ("NAND\n"); 95 break; 96 } 97 98 return 0; 99 } 100 101 phys_size_t 102 initdram(int board_type) 103 { 104 phys_size_t dram_size = 0; 105 106 puts("Initializing...."); 107 108 #ifdef CONFIG_SPD_EEPROM 109 dram_size = fsl_ddr_sdram(); 110 #else 111 dram_size = fixed_sdram(); 112 #endif 113 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 114 dram_size *= 0x100000; 115 116 puts(" DDR: "); 117 return dram_size; 118 } 119 120 #if !defined(CONFIG_SPD_EEPROM) 121 /* 122 * Fixed sdram init -- doesn't use serial presence detect. 123 */ 124 125 phys_size_t fixed_sdram (void) 126 { 127 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 128 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 129 uint d_init; 130 131 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 132 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 133 134 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 135 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 136 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 137 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 138 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 139 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 140 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 141 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 142 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 143 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 144 145 #if defined (CONFIG_DDR_ECC) 146 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 147 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 148 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 149 #endif 150 asm("sync;isync"); 151 152 udelay(500); 153 154 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 155 156 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 157 d_init = 1; 158 debug("DDR - 1st controller: memory initializing\n"); 159 /* 160 * Poll until memory is initialized. 161 * 512 Meg at 400 might hit this 200 times or so. 162 */ 163 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 164 udelay(1000); 165 } 166 debug("DDR: memory initialized\n\n"); 167 asm("sync; isync"); 168 udelay(500); 169 #endif 170 171 return 512 * 1024 * 1024; 172 } 173 174 #endif 175 176 #ifdef CONFIG_PCI1 177 static struct pci_controller pci1_hose; 178 #endif 179 180 #ifdef CONFIG_PCIE1 181 static struct pci_controller pcie1_hose; 182 #endif 183 184 #ifdef CONFIG_PCIE2 185 static struct pci_controller pcie2_hose; 186 #endif 187 188 #ifdef CONFIG_PCIE3 189 static struct pci_controller pcie3_hose; 190 #endif 191 192 #ifdef CONFIG_PCI 193 void pci_init_board(void) 194 { 195 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 196 struct fsl_pci_info pci_info[4]; 197 u32 devdisr, pordevsr, io_sel, sdrs2_io_sel; 198 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 199 int first_free_busno = 0; 200 int num = 0; 201 202 int pcie_ep, pcie_configured; 203 204 devdisr = in_be32(&gur->devdisr); 205 pordevsr = in_be32(&gur->pordevsr); 206 porpllsr = in_be32(&gur->porpllsr); 207 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 208 sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 209 210 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n", 211 devdisr, sdrs2_io_sel, io_sel); 212 213 if (sdrs2_io_sel == 7) 214 printf(" Serdes2 disalbed\n"); 215 else if (sdrs2_io_sel == 4) { 216 printf(" eTSEC1 is in sgmii mode.\n"); 217 printf(" eTSEC3 is in sgmii mode.\n"); 218 } else if (sdrs2_io_sel == 6) 219 printf(" eTSEC1 is in sgmii mode.\n"); 220 221 puts("\n"); 222 #ifdef CONFIG_PCIE3 223 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); 224 225 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 226 SET_STD_PCIE_INFO(pci_info[num], 3); 227 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); 228 printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n", 229 pcie_ep ? "Endpoint" : "Root Complex", 230 pci_info[num].regs); 231 first_free_busno = fsl_pci_init_port(&pci_info[num++], 232 &pcie3_hose, first_free_busno); 233 } else { 234 printf (" PCIE3: disabled\n"); 235 } 236 237 puts("\n"); 238 #else 239 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 240 #endif 241 242 #ifdef CONFIG_PCIE1 243 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 244 245 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 246 SET_STD_PCIE_INFO(pci_info[num], 1); 247 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 248 printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n", 249 pcie_ep ? "Endpoint" : "Root Complex", 250 pci_info[num].regs); 251 first_free_busno = fsl_pci_init_port(&pci_info[num++], 252 &pcie1_hose, first_free_busno); 253 } else { 254 printf (" PCIE1: disabled\n"); 255 } 256 257 puts("\n"); 258 #else 259 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 260 #endif 261 262 #ifdef CONFIG_PCIE2 263 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 264 265 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ 266 SET_STD_PCIE_INFO(pci_info[num], 2); 267 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 268 printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n", 269 pcie_ep ? "Endpoint" : "Root Complex", 270 pci_info[num].regs); 271 first_free_busno = fsl_pci_init_port(&pci_info[num++], 272 &pcie2_hose, first_free_busno); 273 } else { 274 printf (" PCIE2: disabled\n"); 275 } 276 277 puts("\n"); 278 #else 279 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 280 #endif 281 282 #ifdef CONFIG_PCI1 283 pci_speed = 66666000; 284 pci_32 = 1; 285 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 286 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 287 288 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 289 SET_STD_PCI_INFO(pci_info[num], 1); 290 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 291 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 292 (pci_32) ? 32 : 64, 293 (pci_speed == 33333000) ? "33" : 294 (pci_speed == 66666000) ? "66" : "unknown", 295 pci_clk_sel ? "sync" : "async", 296 pci_agent ? "agent" : "host", 297 pci_arb ? "arbiter" : "external-arbiter", 298 pci_info[num].regs); 299 300 first_free_busno = fsl_pci_init_port(&pci_info[num++], 301 &pci1_hose, first_free_busno); 302 } else { 303 printf (" PCI: disabled\n"); 304 } 305 306 puts("\n"); 307 #else 308 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 309 #endif 310 } 311 #endif 312 313 int board_early_init_r(void) 314 { 315 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 316 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 317 318 /* 319 * Remap Boot flash + PROMJET region to caching-inhibited 320 * so that flash can be erased properly. 321 */ 322 323 /* Flush d-cache and invalidate i-cache of any FLASH data */ 324 flush_dcache(); 325 invalidate_icache(); 326 327 /* invalidate existing TLB entry for flash + promjet */ 328 disable_tlb(flash_esel); 329 330 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 331 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 332 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 333 334 return 0; 335 } 336 337 #ifdef CONFIG_GET_CLK_FROM_ICS307 338 /* decode S[0-2] to Output Divider (OD) */ 339 static unsigned char 340 ics307_S_to_OD[] = { 341 10, 2, 8, 4, 5, 7, 3, 6 342 }; 343 344 /* Calculate frequency being generated by ICS307-02 clock chip based upon 345 * the control bytes being programmed into it. */ 346 /* XXX: This function should probably go into a common library */ 347 static unsigned long 348 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 349 { 350 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 351 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 352 unsigned long RDW = cw2 & 0x7F; 353 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 354 unsigned long freq; 355 356 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 357 358 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 359 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 360 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 361 * 362 * R6:R0 = Reference Divider Word (RDW) 363 * V8:V0 = VCO Divider Word (VDW) 364 * S2:S0 = Output Divider Select (OD) 365 * F1:F0 = Function of CLK2 Output 366 * TTL = duty cycle 367 * C1:C0 = internal load capacitance for cyrstal 368 */ 369 370 /* Adding 1 to get a "nicely" rounded number, but this needs 371 * more tweaking to get a "properly" rounded number. */ 372 373 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 374 375 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 376 freq); 377 return freq; 378 } 379 380 unsigned long 381 get_board_sys_clk(ulong dummy) 382 { 383 u8 *pixis_base = (u8 *)PIXIS_BASE; 384 385 return ics307_clk_freq ( 386 in_8(pixis_base + PIXIS_VSYSCLK0), 387 in_8(pixis_base + PIXIS_VSYSCLK1), 388 in_8(pixis_base + PIXIS_VSYSCLK2) 389 ); 390 } 391 392 unsigned long 393 get_board_ddr_clk(ulong dummy) 394 { 395 u8 *pixis_base = (u8 *)PIXIS_BASE; 396 397 return ics307_clk_freq ( 398 in_8(pixis_base + PIXIS_VDDRCLK0), 399 in_8(pixis_base + PIXIS_VDDRCLK1), 400 in_8(pixis_base + PIXIS_VDDRCLK2) 401 ); 402 } 403 #else 404 unsigned long 405 get_board_sys_clk(ulong dummy) 406 { 407 u8 i; 408 ulong val = 0; 409 u8 *pixis_base = (u8 *)PIXIS_BASE; 410 411 i = in_8(pixis_base + PIXIS_SPD); 412 i &= 0x07; 413 414 switch (i) { 415 case 0: 416 val = 33333333; 417 break; 418 case 1: 419 val = 40000000; 420 break; 421 case 2: 422 val = 50000000; 423 break; 424 case 3: 425 val = 66666666; 426 break; 427 case 4: 428 val = 83333333; 429 break; 430 case 5: 431 val = 100000000; 432 break; 433 case 6: 434 val = 133333333; 435 break; 436 case 7: 437 val = 166666666; 438 break; 439 } 440 441 return val; 442 } 443 444 unsigned long 445 get_board_ddr_clk(ulong dummy) 446 { 447 u8 i; 448 ulong val = 0; 449 u8 *pixis_base = (u8 *)PIXIS_BASE; 450 451 i = in_8(pixis_base + PIXIS_SPD); 452 i &= 0x38; 453 i >>= 3; 454 455 switch (i) { 456 case 0: 457 val = 33333333; 458 break; 459 case 1: 460 val = 40000000; 461 break; 462 case 2: 463 val = 50000000; 464 break; 465 case 3: 466 val = 66666666; 467 break; 468 case 4: 469 val = 83333333; 470 break; 471 case 5: 472 val = 100000000; 473 break; 474 case 6: 475 val = 133333333; 476 break; 477 case 7: 478 val = 166666666; 479 break; 480 } 481 return val; 482 } 483 #endif 484 485 int sata_initialize(void) 486 { 487 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 488 uint sdrs2_io_sel = 489 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 490 if (sdrs2_io_sel & 0x04) 491 return 1; 492 493 return __sata_initialize(); 494 } 495 496 int board_eth_init(bd_t *bis) 497 { 498 #ifdef CONFIG_TSEC_ENET 499 struct tsec_info_struct tsec_info[2]; 500 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 501 int num = 0; 502 uint sdrs2_io_sel = 503 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 504 505 #ifdef CONFIG_TSEC1 506 SET_STD_TSEC_INFO(tsec_info[num], 1); 507 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { 508 tsec_info[num].phyaddr = 0; 509 tsec_info[num].flags |= TSEC_SGMII; 510 } 511 num++; 512 #endif 513 #ifdef CONFIG_TSEC3 514 SET_STD_TSEC_INFO(tsec_info[num], 3); 515 if (sdrs2_io_sel == 4) { 516 tsec_info[num].phyaddr = 1; 517 tsec_info[num].flags |= TSEC_SGMII; 518 } 519 num++; 520 #endif 521 522 if (!num) { 523 printf("No TSECs initialized\n"); 524 return 0; 525 } 526 527 #ifdef CONFIG_FSL_SGMII_RISER 528 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) 529 fsl_sgmii_riser_init(tsec_info, num); 530 #endif 531 532 tsec_eth_init(bis, tsec_info, num); 533 #endif 534 return pci_eth_init(bis); 535 } 536 537 #if defined(CONFIG_OF_BOARD_SETUP) 538 void ft_board_setup(void *blob, bd_t *bd) 539 { 540 ft_cpu_setup(blob, bd); 541 542 #ifdef CONFIG_PCI1 543 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 544 #endif 545 #ifdef CONFIG_PCIE2 546 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 547 #endif 548 #ifdef CONFIG_PCIE2 549 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 550 #endif 551 #ifdef CONFIG_PCIE1 552 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); 553 #endif 554 #ifdef CONFIG_FSL_SGMII_RISER 555 fsl_sgmii_riser_fdt_fixup(blob); 556 #endif 557 } 558 #endif 559