1 /* 2 * Copyright 2008 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <spd_sdram.h> 37 #include <fdt_support.h> 38 #include <tsec.h> 39 #include <netdev.h> 40 #include <sata.h> 41 42 #include "../common/pixis.h" 43 #include "../common/sgmii_riser.h" 44 45 phys_size_t fixed_sdram(void); 46 47 int board_early_init_f (void) 48 { 49 #ifdef CONFIG_MMC 50 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 51 52 setbits_be32(&gur->pmuxcr, 53 (MPC85xx_PMUXCR_SD_DATA | 54 MPC85xx_PMUXCR_SDHC_CD | 55 MPC85xx_PMUXCR_SDHC_WP)); 56 57 #endif 58 return 0; 59 } 60 61 int checkboard (void) 62 { 63 u8 vboot; 64 u8 *pixis_base = (u8 *)PIXIS_BASE; 65 66 puts("Board: MPC8536DS "); 67 #ifdef CONFIG_PHYS_64BIT 68 puts("(36-bit addrmap) "); 69 #endif 70 71 printf ("Sys ID: 0x%02x, " 72 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 73 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 74 in_8(pixis_base + PIXIS_PVER)); 75 76 vboot = in_8(pixis_base + PIXIS_VBOOT); 77 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 78 case PIXIS_VBOOT_LBMAP_NOR0: 79 puts ("vBank: 0\n"); 80 break; 81 case PIXIS_VBOOT_LBMAP_NOR1: 82 puts ("vBank: 1\n"); 83 break; 84 case PIXIS_VBOOT_LBMAP_NOR2: 85 puts ("vBank: 2\n"); 86 break; 87 case PIXIS_VBOOT_LBMAP_NOR3: 88 puts ("vBank: 3\n"); 89 break; 90 case PIXIS_VBOOT_LBMAP_PJET: 91 puts ("Promjet\n"); 92 break; 93 case PIXIS_VBOOT_LBMAP_NAND: 94 puts ("NAND\n"); 95 break; 96 } 97 98 return 0; 99 } 100 101 phys_size_t 102 initdram(int board_type) 103 { 104 phys_size_t dram_size = 0; 105 106 puts("Initializing...."); 107 108 #ifdef CONFIG_SPD_EEPROM 109 dram_size = fsl_ddr_sdram(); 110 #else 111 dram_size = fixed_sdram(); 112 #endif 113 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 114 dram_size *= 0x100000; 115 116 puts(" DDR: "); 117 return dram_size; 118 } 119 120 #if !defined(CONFIG_SPD_EEPROM) 121 /* 122 * Fixed sdram init -- doesn't use serial presence detect. 123 */ 124 125 phys_size_t fixed_sdram (void) 126 { 127 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 128 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 129 uint d_init; 130 131 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 132 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 133 134 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 135 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 136 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 137 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 138 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 139 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 140 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 141 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 142 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 143 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 144 145 #if defined (CONFIG_DDR_ECC) 146 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 147 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 148 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 149 #endif 150 asm("sync;isync"); 151 152 udelay(500); 153 154 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 155 156 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 157 d_init = 1; 158 debug("DDR - 1st controller: memory initializing\n"); 159 /* 160 * Poll until memory is initialized. 161 * 512 Meg at 400 might hit this 200 times or so. 162 */ 163 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 164 udelay(1000); 165 } 166 debug("DDR: memory initialized\n\n"); 167 asm("sync; isync"); 168 udelay(500); 169 #endif 170 171 return 512 * 1024 * 1024; 172 } 173 174 #endif 175 176 #ifdef CONFIG_PCI1 177 static struct pci_controller pci1_hose; 178 #endif 179 180 #ifdef CONFIG_PCIE1 181 static struct pci_controller pcie1_hose; 182 #endif 183 184 #ifdef CONFIG_PCIE2 185 static struct pci_controller pcie2_hose; 186 #endif 187 188 #ifdef CONFIG_PCIE3 189 static struct pci_controller pcie3_hose; 190 #endif 191 192 int first_free_busno=0; 193 194 void 195 pci_init_board(void) 196 { 197 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 198 uint devdisr = gur->devdisr; 199 uint sdrs2_io_sel = 200 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 201 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 202 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 203 204 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ 205 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); 206 207 if (sdrs2_io_sel == 7) 208 printf(" Serdes2 disalbed\n"); 209 else if (sdrs2_io_sel == 4) { 210 printf(" eTSEC1 is in sgmii mode.\n"); 211 printf(" eTSEC3 is in sgmii mode.\n"); 212 } else if (sdrs2_io_sel == 6) 213 printf(" eTSEC1 is in sgmii mode.\n"); 214 215 #ifdef CONFIG_PCIE3 216 { 217 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 218 struct pci_controller *hose = &pcie3_hose; 219 int pcie_ep = (host_agent == 1); 220 int pcie_configured = (io_sel == 7); 221 struct pci_region *r = hose->regions; 222 223 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 224 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", 225 pcie_ep ? "End Point" : "Root Complex", 226 (uint)pci); 227 if (pci->pme_msg_det) { 228 pci->pme_msg_det = 0xffffffff; 229 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 230 } 231 printf ("\n"); 232 233 /* inbound */ 234 r += fsl_pci_setup_inbound_windows(r); 235 236 /* outbound memory */ 237 pci_set_region(r++, 238 CONFIG_SYS_PCIE3_MEM_BUS, 239 CONFIG_SYS_PCIE3_MEM_PHYS, 240 CONFIG_SYS_PCIE3_MEM_SIZE, 241 PCI_REGION_MEM); 242 243 /* outbound io */ 244 pci_set_region(r++, 245 CONFIG_SYS_PCIE3_IO_BUS, 246 CONFIG_SYS_PCIE3_IO_PHYS, 247 CONFIG_SYS_PCIE3_IO_SIZE, 248 PCI_REGION_IO); 249 250 hose->region_count = r - hose->regions; 251 252 hose->first_busno=first_free_busno; 253 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 254 255 fsl_pci_init(hose); 256 257 first_free_busno=hose->last_busno+1; 258 printf (" PCIE3 on bus %02x - %02x\n", 259 hose->first_busno,hose->last_busno); 260 } else { 261 printf (" PCIE3: disabled\n"); 262 } 263 264 } 265 #else 266 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 267 #endif 268 269 #ifdef CONFIG_PCIE1 270 { 271 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 272 struct pci_controller *hose = &pcie1_hose; 273 int pcie_ep = (host_agent == 5); 274 int pcie_configured = (io_sel == 2 || io_sel == 3 275 || io_sel == 5 || io_sel == 7); 276 struct pci_region *r = hose->regions; 277 278 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 279 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", 280 pcie_ep ? "End Point" : "Root Complex", 281 (uint)pci); 282 if (pci->pme_msg_det) { 283 pci->pme_msg_det = 0xffffffff; 284 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 285 } 286 printf ("\n"); 287 288 /* inbound */ 289 r += fsl_pci_setup_inbound_windows(r); 290 291 /* outbound memory */ 292 pci_set_region(r++, 293 CONFIG_SYS_PCIE1_MEM_BUS, 294 CONFIG_SYS_PCIE1_MEM_PHYS, 295 CONFIG_SYS_PCIE1_MEM_SIZE, 296 PCI_REGION_MEM); 297 298 /* outbound io */ 299 pci_set_region(r++, 300 CONFIG_SYS_PCIE1_IO_BUS, 301 CONFIG_SYS_PCIE1_IO_PHYS, 302 CONFIG_SYS_PCIE1_IO_SIZE, 303 PCI_REGION_IO); 304 305 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 306 /* outbound memory */ 307 pci_set_region(r++, 308 CONFIG_SYS_PCIE1_MEM_BUS2, 309 CONFIG_SYS_PCIE1_MEM_PHYS2, 310 CONFIG_SYS_PCIE1_MEM_SIZE2, 311 PCI_REGION_MEM); 312 #endif 313 hose->region_count = r - hose->regions; 314 hose->first_busno=first_free_busno; 315 316 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 317 318 fsl_pci_init(hose); 319 320 first_free_busno=hose->last_busno+1; 321 printf(" PCIE1 on bus %02x - %02x\n", 322 hose->first_busno,hose->last_busno); 323 324 } else { 325 printf (" PCIE1: disabled\n"); 326 } 327 328 } 329 #else 330 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 331 #endif 332 333 #ifdef CONFIG_PCIE2 334 { 335 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 336 struct pci_controller *hose = &pcie2_hose; 337 int pcie_ep = (host_agent == 3); 338 int pcie_configured = (io_sel == 5 || io_sel == 7); 339 struct pci_region *r = hose->regions; 340 341 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 342 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", 343 pcie_ep ? "End Point" : "Root Complex", 344 (uint)pci); 345 if (pci->pme_msg_det) { 346 pci->pme_msg_det = 0xffffffff; 347 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 348 } 349 printf ("\n"); 350 351 /* inbound */ 352 r += fsl_pci_setup_inbound_windows(r); 353 354 /* outbound memory */ 355 pci_set_region(r++, 356 CONFIG_SYS_PCIE2_MEM_BUS, 357 CONFIG_SYS_PCIE2_MEM_PHYS, 358 CONFIG_SYS_PCIE2_MEM_SIZE, 359 PCI_REGION_MEM); 360 361 /* outbound io */ 362 pci_set_region(r++, 363 CONFIG_SYS_PCIE2_IO_BUS, 364 CONFIG_SYS_PCIE2_IO_PHYS, 365 CONFIG_SYS_PCIE2_IO_SIZE, 366 PCI_REGION_IO); 367 368 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 369 /* outbound memory */ 370 pci_set_region(r++, 371 CONFIG_SYS_PCIE2_MEM_BUS2, 372 CONFIG_SYS_PCIE2_MEM_PHYS2, 373 CONFIG_SYS_PCIE2_MEM_SIZE2, 374 PCI_REGION_MEM); 375 #endif 376 hose->region_count = r - hose->regions; 377 hose->first_busno=first_free_busno; 378 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 379 380 fsl_pci_init(hose); 381 first_free_busno=hose->last_busno+1; 382 printf (" PCIE2 on bus %02x - %02x\n", 383 hose->first_busno,hose->last_busno); 384 385 } else { 386 printf (" PCIE2: disabled\n"); 387 } 388 389 } 390 #else 391 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 392 #endif 393 394 395 #ifdef CONFIG_PCI1 396 { 397 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 398 struct pci_controller *hose = &pci1_hose; 399 struct pci_region *r = hose->regions; 400 401 uint pci_agent = (host_agent == 6); 402 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 403 uint pci_32 = 1; 404 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 405 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 406 407 408 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 409 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 410 (pci_32) ? 32 : 64, 411 (pci_speed == 33333000) ? "33" : 412 (pci_speed == 66666000) ? "66" : "unknown", 413 pci_clk_sel ? "sync" : "async", 414 pci_agent ? "agent" : "host", 415 pci_arb ? "arbiter" : "external-arbiter", 416 (uint)pci 417 ); 418 419 /* inbound */ 420 r += fsl_pci_setup_inbound_windows(r); 421 422 /* outbound memory */ 423 pci_set_region(r++, 424 CONFIG_SYS_PCI1_MEM_BUS, 425 CONFIG_SYS_PCI1_MEM_PHYS, 426 CONFIG_SYS_PCI1_MEM_SIZE, 427 PCI_REGION_MEM); 428 429 /* outbound io */ 430 pci_set_region(r++, 431 CONFIG_SYS_PCI1_IO_BUS, 432 CONFIG_SYS_PCI1_IO_PHYS, 433 CONFIG_SYS_PCI1_IO_SIZE, 434 PCI_REGION_IO); 435 436 #ifdef CONFIG_SYS_PCI1_MEM_BUS2 437 /* outbound memory */ 438 pci_set_region(r++, 439 CONFIG_SYS_PCI1_MEM_BUS2, 440 CONFIG_SYS_PCI1_MEM_PHYS2, 441 CONFIG_SYS_PCI1_MEM_SIZE2, 442 PCI_REGION_MEM); 443 #endif 444 hose->region_count = r - hose->regions; 445 hose->first_busno=first_free_busno; 446 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 447 448 fsl_pci_init(hose); 449 first_free_busno=hose->last_busno+1; 450 printf ("PCI on bus %02x - %02x\n", 451 hose->first_busno,hose->last_busno); 452 } else { 453 printf (" PCI: disabled\n"); 454 } 455 } 456 #else 457 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 458 #endif 459 } 460 461 462 int board_early_init_r(void) 463 { 464 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 465 const u8 flash_esel = 1; 466 467 /* 468 * Remap Boot flash + PROMJET region to caching-inhibited 469 * so that flash can be erased properly. 470 */ 471 472 /* Flush d-cache and invalidate i-cache of any FLASH data */ 473 flush_dcache(); 474 invalidate_icache(); 475 476 /* invalidate existing TLB entry for flash + promjet */ 477 disable_tlb(flash_esel); 478 479 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 480 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 481 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 482 483 return 0; 484 } 485 486 #ifdef CONFIG_GET_CLK_FROM_ICS307 487 /* decode S[0-2] to Output Divider (OD) */ 488 static unsigned char 489 ics307_S_to_OD[] = { 490 10, 2, 8, 4, 5, 7, 3, 6 491 }; 492 493 /* Calculate frequency being generated by ICS307-02 clock chip based upon 494 * the control bytes being programmed into it. */ 495 /* XXX: This function should probably go into a common library */ 496 static unsigned long 497 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 498 { 499 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 500 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 501 unsigned long RDW = cw2 & 0x7F; 502 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 503 unsigned long freq; 504 505 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 506 507 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 508 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 509 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 510 * 511 * R6:R0 = Reference Divider Word (RDW) 512 * V8:V0 = VCO Divider Word (VDW) 513 * S2:S0 = Output Divider Select (OD) 514 * F1:F0 = Function of CLK2 Output 515 * TTL = duty cycle 516 * C1:C0 = internal load capacitance for cyrstal 517 */ 518 519 /* Adding 1 to get a "nicely" rounded number, but this needs 520 * more tweaking to get a "properly" rounded number. */ 521 522 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 523 524 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 525 freq); 526 return freq; 527 } 528 529 unsigned long 530 get_board_sys_clk(ulong dummy) 531 { 532 u8 *pixis_base = (u8 *)PIXIS_BASE; 533 534 return ics307_clk_freq ( 535 in_8(pixis_base + PIXIS_VSYSCLK0), 536 in_8(pixis_base + PIXIS_VSYSCLK1), 537 in_8(pixis_base + PIXIS_VSYSCLK2) 538 ); 539 } 540 541 unsigned long 542 get_board_ddr_clk(ulong dummy) 543 { 544 u8 *pixis_base = (u8 *)PIXIS_BASE; 545 546 return ics307_clk_freq ( 547 in_8(pixis_base + PIXIS_VDDRCLK0), 548 in_8(pixis_base + PIXIS_VDDRCLK1), 549 in_8(pixis_base + PIXIS_VDDRCLK2) 550 ); 551 } 552 #else 553 unsigned long 554 get_board_sys_clk(ulong dummy) 555 { 556 u8 i; 557 ulong val = 0; 558 u8 *pixis_base = (u8 *)PIXIS_BASE; 559 560 i = in_8(pixis_base + PIXIS_SPD); 561 i &= 0x07; 562 563 switch (i) { 564 case 0: 565 val = 33333333; 566 break; 567 case 1: 568 val = 40000000; 569 break; 570 case 2: 571 val = 50000000; 572 break; 573 case 3: 574 val = 66666666; 575 break; 576 case 4: 577 val = 83333333; 578 break; 579 case 5: 580 val = 100000000; 581 break; 582 case 6: 583 val = 133333333; 584 break; 585 case 7: 586 val = 166666666; 587 break; 588 } 589 590 return val; 591 } 592 593 unsigned long 594 get_board_ddr_clk(ulong dummy) 595 { 596 u8 i; 597 ulong val = 0; 598 u8 *pixis_base = (u8 *)PIXIS_BASE; 599 600 i = in_8(pixis_base + PIXIS_SPD); 601 i &= 0x38; 602 i >>= 3; 603 604 switch (i) { 605 case 0: 606 val = 33333333; 607 break; 608 case 1: 609 val = 40000000; 610 break; 611 case 2: 612 val = 50000000; 613 break; 614 case 3: 615 val = 66666666; 616 break; 617 case 4: 618 val = 83333333; 619 break; 620 case 5: 621 val = 100000000; 622 break; 623 case 6: 624 val = 133333333; 625 break; 626 case 7: 627 val = 166666666; 628 break; 629 } 630 return val; 631 } 632 #endif 633 634 int sata_initialize(void) 635 { 636 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 637 uint sdrs2_io_sel = 638 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 639 if (sdrs2_io_sel & 0x04) 640 return 1; 641 642 return __sata_initialize(); 643 } 644 645 int board_eth_init(bd_t *bis) 646 { 647 #ifdef CONFIG_TSEC_ENET 648 struct tsec_info_struct tsec_info[2]; 649 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 650 int num = 0; 651 uint sdrs2_io_sel = 652 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 653 654 #ifdef CONFIG_TSEC1 655 SET_STD_TSEC_INFO(tsec_info[num], 1); 656 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { 657 tsec_info[num].phyaddr = 0; 658 tsec_info[num].flags |= TSEC_SGMII; 659 } 660 num++; 661 #endif 662 #ifdef CONFIG_TSEC3 663 SET_STD_TSEC_INFO(tsec_info[num], 3); 664 if (sdrs2_io_sel == 4) { 665 tsec_info[num].phyaddr = 1; 666 tsec_info[num].flags |= TSEC_SGMII; 667 } 668 num++; 669 #endif 670 671 if (!num) { 672 printf("No TSECs initialized\n"); 673 return 0; 674 } 675 676 #ifdef CONFIG_FSL_SGMII_RISER 677 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) 678 fsl_sgmii_riser_init(tsec_info, num); 679 #endif 680 681 tsec_eth_init(bis, tsec_info, num); 682 #endif 683 return pci_eth_init(bis); 684 } 685 686 #if defined(CONFIG_OF_BOARD_SETUP) 687 void ft_board_setup(void *blob, bd_t *bd) 688 { 689 ft_cpu_setup(blob, bd); 690 691 #ifdef CONFIG_PCI1 692 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 693 #endif 694 #ifdef CONFIG_PCIE2 695 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 696 #endif 697 #ifdef CONFIG_PCIE2 698 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 699 #endif 700 #ifdef CONFIG_PCIE1 701 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); 702 #endif 703 #ifdef CONFIG_FSL_SGMII_RISER 704 fsl_sgmii_riser_fdt_fixup(blob); 705 #endif 706 } 707 #endif 708