1 /* 2 * Copyright 2008 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/immap_fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <spd_sdram.h> 37 #include <fdt_support.h> 38 #include <tsec.h> 39 #include <netdev.h> 40 41 #include "../common/pixis.h" 42 #include "../common/sgmii_riser.h" 43 44 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 45 extern void ddr_enable_ecc(unsigned int dram_size); 46 #endif 47 48 phys_size_t fixed_sdram(void); 49 50 int checkboard (void) 51 { 52 printf ("Board: MPC8536DS, System ID: 0x%02x, " 53 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 54 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 55 in8(PIXIS_BASE + PIXIS_PVER)); 56 return 0; 57 } 58 59 phys_size_t 60 initdram(int board_type) 61 { 62 phys_size_t dram_size = 0; 63 64 puts("Initializing...."); 65 66 #ifdef CONFIG_SPD_EEPROM 67 dram_size = fsl_ddr_sdram(); 68 69 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 70 71 dram_size *= 0x100000; 72 #else 73 dram_size = fixed_sdram(); 74 #endif 75 76 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 77 /* 78 * Initialize and enable DDR ECC. 79 */ 80 ddr_enable_ecc(dram_size); 81 #endif 82 puts(" DDR: "); 83 return dram_size; 84 } 85 86 #if !defined(CONFIG_SPD_EEPROM) 87 /* 88 * Fixed sdram init -- doesn't use serial presence detect. 89 */ 90 91 phys_size_t fixed_sdram (void) 92 { 93 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 94 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 95 uint d_init; 96 97 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 98 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 99 100 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 101 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 102 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 103 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 104 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 105 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 106 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 107 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 108 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 109 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 110 111 #if defined (CONFIG_DDR_ECC) 112 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 113 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 114 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 115 #endif 116 asm("sync;isync"); 117 118 udelay(500); 119 120 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 121 122 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 123 d_init = 1; 124 debug("DDR - 1st controller: memory initializing\n"); 125 /* 126 * Poll until memory is initialized. 127 * 512 Meg at 400 might hit this 200 times or so. 128 */ 129 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 130 udelay(1000); 131 } 132 debug("DDR: memory initialized\n\n"); 133 asm("sync; isync"); 134 udelay(500); 135 #endif 136 137 return 512 * 1024 * 1024; 138 } 139 140 #endif 141 142 #ifdef CONFIG_PCI1 143 static struct pci_controller pci1_hose; 144 #endif 145 146 #ifdef CONFIG_PCIE1 147 static struct pci_controller pcie1_hose; 148 #endif 149 150 #ifdef CONFIG_PCIE2 151 static struct pci_controller pcie2_hose; 152 #endif 153 154 #ifdef CONFIG_PCIE3 155 static struct pci_controller pcie3_hose; 156 #endif 157 158 int first_free_busno=0; 159 160 void 161 pci_init_board(void) 162 { 163 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 164 uint devdisr = gur->devdisr; 165 uint sdrs2_io_sel = 166 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 167 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 168 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 169 170 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ 171 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); 172 173 if (sdrs2_io_sel == 7) 174 printf(" Serdes2 disalbed\n"); 175 else if (sdrs2_io_sel == 4) { 176 printf(" eTSEC1 is in sgmii mode.\n"); 177 printf(" eTSEC3 is in sgmii mode.\n"); 178 } else if (sdrs2_io_sel == 6) 179 printf(" eTSEC1 is in sgmii mode.\n"); 180 181 #ifdef CONFIG_PCIE3 182 { 183 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 184 extern void fsl_pci_init(struct pci_controller *hose); 185 struct pci_controller *hose = &pcie3_hose; 186 int pcie_ep = (host_agent == 1); 187 int pcie_configured = (io_sel == 7); 188 189 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 190 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", 191 pcie_ep ? "End Point" : "Root Complex", 192 (uint)pci); 193 if (pci->pme_msg_det) { 194 pci->pme_msg_det = 0xffffffff; 195 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 196 } 197 printf ("\n"); 198 199 /* inbound */ 200 pci_set_region(hose->regions + 0, 201 CONFIG_SYS_PCI_MEMORY_BUS, 202 CONFIG_SYS_PCI_MEMORY_PHYS, 203 CONFIG_SYS_PCI_MEMORY_SIZE, 204 PCI_REGION_MEM | PCI_REGION_MEMORY); 205 206 /* outbound memory */ 207 pci_set_region(hose->regions + 1, 208 CONFIG_SYS_PCIE3_MEM_BASE, 209 CONFIG_SYS_PCIE3_MEM_PHYS, 210 CONFIG_SYS_PCIE3_MEM_SIZE, 211 PCI_REGION_MEM); 212 213 /* outbound io */ 214 pci_set_region(hose->regions + 2, 215 CONFIG_SYS_PCIE3_IO_BASE, 216 CONFIG_SYS_PCIE3_IO_PHYS, 217 CONFIG_SYS_PCIE3_IO_SIZE, 218 PCI_REGION_IO); 219 220 hose->region_count = 3; 221 222 hose->first_busno=first_free_busno; 223 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 224 225 fsl_pci_init(hose); 226 227 first_free_busno=hose->last_busno+1; 228 printf (" PCIE3 on bus %02x - %02x\n", 229 hose->first_busno,hose->last_busno); 230 } else { 231 printf (" PCIE3: disabled\n"); 232 } 233 234 } 235 #else 236 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 237 #endif 238 239 #ifdef CONFIG_PCIE1 240 { 241 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 242 extern void fsl_pci_init(struct pci_controller *hose); 243 struct pci_controller *hose = &pcie1_hose; 244 int pcie_ep = (host_agent == 5); 245 int pcie_configured = (io_sel == 2 || io_sel == 3 246 || io_sel == 5 || io_sel == 7); 247 248 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 249 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", 250 pcie_ep ? "End Point" : "Root Complex", 251 (uint)pci); 252 if (pci->pme_msg_det) { 253 pci->pme_msg_det = 0xffffffff; 254 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 255 } 256 printf ("\n"); 257 258 /* inbound */ 259 pci_set_region(hose->regions + 0, 260 CONFIG_SYS_PCI_MEMORY_BUS, 261 CONFIG_SYS_PCI_MEMORY_PHYS, 262 CONFIG_SYS_PCI_MEMORY_SIZE, 263 PCI_REGION_MEM | PCI_REGION_MEMORY); 264 265 /* outbound memory */ 266 pci_set_region(hose->regions + 1, 267 CONFIG_SYS_PCIE1_MEM_BASE, 268 CONFIG_SYS_PCIE1_MEM_PHYS, 269 CONFIG_SYS_PCIE1_MEM_SIZE, 270 PCI_REGION_MEM); 271 272 /* outbound io */ 273 pci_set_region(hose->regions + 2, 274 CONFIG_SYS_PCIE1_IO_BASE, 275 CONFIG_SYS_PCIE1_IO_PHYS, 276 CONFIG_SYS_PCIE1_IO_SIZE, 277 PCI_REGION_IO); 278 279 hose->region_count = 3; 280 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2 281 /* outbound memory */ 282 pci_set_region(hose->regions + 3, 283 CONFIG_SYS_PCIE1_MEM_BASE2, 284 CONFIG_SYS_PCIE1_MEM_PHYS2, 285 CONFIG_SYS_PCIE1_MEM_SIZE2, 286 PCI_REGION_MEM); 287 hose->region_count++; 288 #endif 289 hose->first_busno=first_free_busno; 290 291 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 292 293 fsl_pci_init(hose); 294 295 first_free_busno=hose->last_busno+1; 296 printf(" PCIE1 on bus %02x - %02x\n", 297 hose->first_busno,hose->last_busno); 298 299 } else { 300 printf (" PCIE1: disabled\n"); 301 } 302 303 } 304 #else 305 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 306 #endif 307 308 #ifdef CONFIG_PCIE2 309 { 310 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 311 extern void fsl_pci_init(struct pci_controller *hose); 312 struct pci_controller *hose = &pcie2_hose; 313 int pcie_ep = (host_agent == 3); 314 int pcie_configured = (io_sel == 5 || io_sel == 7); 315 316 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 317 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", 318 pcie_ep ? "End Point" : "Root Complex", 319 (uint)pci); 320 if (pci->pme_msg_det) { 321 pci->pme_msg_det = 0xffffffff; 322 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 323 } 324 printf ("\n"); 325 326 /* inbound */ 327 pci_set_region(hose->regions + 0, 328 CONFIG_SYS_PCI_MEMORY_BUS, 329 CONFIG_SYS_PCI_MEMORY_PHYS, 330 CONFIG_SYS_PCI_MEMORY_SIZE, 331 PCI_REGION_MEM | PCI_REGION_MEMORY); 332 333 /* outbound memory */ 334 pci_set_region(hose->regions + 1, 335 CONFIG_SYS_PCIE2_MEM_BASE, 336 CONFIG_SYS_PCIE2_MEM_PHYS, 337 CONFIG_SYS_PCIE2_MEM_SIZE, 338 PCI_REGION_MEM); 339 340 /* outbound io */ 341 pci_set_region(hose->regions + 2, 342 CONFIG_SYS_PCIE2_IO_BASE, 343 CONFIG_SYS_PCIE2_IO_PHYS, 344 CONFIG_SYS_PCIE2_IO_SIZE, 345 PCI_REGION_IO); 346 347 hose->region_count = 3; 348 #ifdef CONFIG_SYS_PCIE2_MEM_BASE2 349 /* outbound memory */ 350 pci_set_region(hose->regions + 3, 351 CONFIG_SYS_PCIE2_MEM_BASE2, 352 CONFIG_SYS_PCIE2_MEM_PHYS2, 353 CONFIG_SYS_PCIE2_MEM_SIZE2, 354 PCI_REGION_MEM); 355 hose->region_count++; 356 #endif 357 hose->first_busno=first_free_busno; 358 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 359 360 fsl_pci_init(hose); 361 first_free_busno=hose->last_busno+1; 362 printf (" PCIE2 on bus %02x - %02x\n", 363 hose->first_busno,hose->last_busno); 364 365 } else { 366 printf (" PCIE2: disabled\n"); 367 } 368 369 } 370 #else 371 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 372 #endif 373 374 375 #ifdef CONFIG_PCI1 376 { 377 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 378 extern void fsl_pci_init(struct pci_controller *hose); 379 struct pci_controller *hose = &pci1_hose; 380 381 uint pci_agent = (host_agent == 6); 382 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 383 uint pci_32 = 1; 384 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 385 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 386 387 388 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 389 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 390 (pci_32) ? 32 : 64, 391 (pci_speed == 33333000) ? "33" : 392 (pci_speed == 66666000) ? "66" : "unknown", 393 pci_clk_sel ? "sync" : "async", 394 pci_agent ? "agent" : "host", 395 pci_arb ? "arbiter" : "external-arbiter", 396 (uint)pci 397 ); 398 399 /* inbound */ 400 pci_set_region(hose->regions + 0, 401 CONFIG_SYS_PCI_MEMORY_BUS, 402 CONFIG_SYS_PCI_MEMORY_PHYS, 403 CONFIG_SYS_PCI_MEMORY_SIZE, 404 PCI_REGION_MEM | PCI_REGION_MEMORY); 405 406 /* outbound memory */ 407 pci_set_region(hose->regions + 1, 408 CONFIG_SYS_PCI1_MEM_BASE, 409 CONFIG_SYS_PCI1_MEM_PHYS, 410 CONFIG_SYS_PCI1_MEM_SIZE, 411 PCI_REGION_MEM); 412 413 /* outbound io */ 414 pci_set_region(hose->regions + 2, 415 CONFIG_SYS_PCI1_IO_BASE, 416 CONFIG_SYS_PCI1_IO_PHYS, 417 CONFIG_SYS_PCI1_IO_SIZE, 418 PCI_REGION_IO); 419 hose->region_count = 3; 420 #ifdef CONFIG_SYS_PCI1_MEM_BASE2 421 /* outbound memory */ 422 pci_set_region(hose->regions + 3, 423 CONFIG_SYS_PCI1_MEM_BASE2, 424 CONFIG_SYS_PCI1_MEM_PHYS2, 425 CONFIG_SYS_PCI1_MEM_SIZE2, 426 PCI_REGION_MEM); 427 hose->region_count++; 428 #endif 429 hose->first_busno=first_free_busno; 430 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 431 432 fsl_pci_init(hose); 433 first_free_busno=hose->last_busno+1; 434 printf ("PCI on bus %02x - %02x\n", 435 hose->first_busno,hose->last_busno); 436 } else { 437 printf (" PCI: disabled\n"); 438 } 439 } 440 #else 441 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 442 #endif 443 } 444 445 446 int board_early_init_r(void) 447 { 448 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 449 const u8 flash_esel = 1; 450 451 /* 452 * Remap Boot flash + PROMJET region to caching-inhibited 453 * so that flash can be erased properly. 454 */ 455 456 /* Flush d-cache and invalidate i-cache of any FLASH data */ 457 flush_dcache(); 458 invalidate_icache(); 459 460 /* invalidate existing TLB entry for flash + promjet */ 461 disable_tlb(flash_esel); 462 463 set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ 464 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 465 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 466 467 return 0; 468 } 469 470 #ifdef CONFIG_GET_CLK_FROM_ICS307 471 /* decode S[0-2] to Output Divider (OD) */ 472 static unsigned char 473 ics307_S_to_OD[] = { 474 10, 2, 8, 4, 5, 7, 3, 6 475 }; 476 477 /* Calculate frequency being generated by ICS307-02 clock chip based upon 478 * the control bytes being programmed into it. */ 479 /* XXX: This function should probably go into a common library */ 480 static unsigned long 481 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 482 { 483 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 484 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 485 unsigned long RDW = cw2 & 0x7F; 486 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 487 unsigned long freq; 488 489 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 490 491 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 492 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 493 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 494 * 495 * R6:R0 = Reference Divider Word (RDW) 496 * V8:V0 = VCO Divider Word (VDW) 497 * S2:S0 = Output Divider Select (OD) 498 * F1:F0 = Function of CLK2 Output 499 * TTL = duty cycle 500 * C1:C0 = internal load capacitance for cyrstal 501 */ 502 503 /* Adding 1 to get a "nicely" rounded number, but this needs 504 * more tweaking to get a "properly" rounded number. */ 505 506 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 507 508 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 509 freq); 510 return freq; 511 } 512 513 unsigned long 514 get_board_sys_clk(ulong dummy) 515 { 516 return ics307_clk_freq ( 517 in8(PIXIS_BASE + PIXIS_VSYSCLK0), 518 in8(PIXIS_BASE + PIXIS_VSYSCLK1), 519 in8(PIXIS_BASE + PIXIS_VSYSCLK2) 520 ); 521 } 522 523 unsigned long 524 get_board_ddr_clk(ulong dummy) 525 { 526 return ics307_clk_freq ( 527 in8(PIXIS_BASE + PIXIS_VDDRCLK0), 528 in8(PIXIS_BASE + PIXIS_VDDRCLK1), 529 in8(PIXIS_BASE + PIXIS_VDDRCLK2) 530 ); 531 } 532 #else 533 unsigned long 534 get_board_sys_clk(ulong dummy) 535 { 536 u8 i; 537 ulong val = 0; 538 539 i = in8(PIXIS_BASE + PIXIS_SPD); 540 i &= 0x07; 541 542 switch (i) { 543 case 0: 544 val = 33333333; 545 break; 546 case 1: 547 val = 40000000; 548 break; 549 case 2: 550 val = 50000000; 551 break; 552 case 3: 553 val = 66666666; 554 break; 555 case 4: 556 val = 83333333; 557 break; 558 case 5: 559 val = 100000000; 560 break; 561 case 6: 562 val = 133333333; 563 break; 564 case 7: 565 val = 166666666; 566 break; 567 } 568 569 return val; 570 } 571 572 unsigned long 573 get_board_ddr_clk(ulong dummy) 574 { 575 u8 i; 576 ulong val = 0; 577 578 i = in8(PIXIS_BASE + PIXIS_SPD); 579 i &= 0x38; 580 i >>= 3; 581 582 switch (i) { 583 case 0: 584 val = 33333333; 585 break; 586 case 1: 587 val = 40000000; 588 break; 589 case 2: 590 val = 50000000; 591 break; 592 case 3: 593 val = 66666666; 594 break; 595 case 4: 596 val = 83333333; 597 break; 598 case 5: 599 val = 100000000; 600 break; 601 case 6: 602 val = 133333333; 603 break; 604 case 7: 605 val = 166666666; 606 break; 607 } 608 return val; 609 } 610 #endif 611 612 int is_sata_supported(void) 613 { 614 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 615 uint devdisr = gur->devdisr; 616 uint sdrs2_io_sel = 617 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 618 if (sdrs2_io_sel & 0x04) 619 return 0; 620 621 return 1; 622 } 623 624 int board_eth_init(bd_t *bis) 625 { 626 #ifdef CONFIG_TSEC_ENET 627 struct tsec_info_struct tsec_info[2]; 628 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 629 int num = 0; 630 uint sdrs2_io_sel = 631 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 632 633 #ifdef CONFIG_TSEC1 634 SET_STD_TSEC_INFO(tsec_info[num], 1); 635 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { 636 tsec_info[num].phyaddr = 0; 637 tsec_info[num].flags |= TSEC_SGMII; 638 } 639 num++; 640 #endif 641 #ifdef CONFIG_TSEC3 642 SET_STD_TSEC_INFO(tsec_info[num], 3); 643 if (sdrs2_io_sel == 4) { 644 tsec_info[num].phyaddr = 1; 645 tsec_info[num].flags |= TSEC_SGMII; 646 } 647 num++; 648 #endif 649 650 if (!num) { 651 printf("No TSECs initialized\n"); 652 return 0; 653 } 654 655 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) 656 fsl_sgmii_riser_init(tsec_info, num); 657 658 tsec_eth_init(bis, tsec_info, num); 659 #endif 660 return pci_eth_init(bis); 661 } 662 663 #if defined(CONFIG_OF_BOARD_SETUP) 664 void 665 ft_board_setup(void *blob, bd_t *bd) 666 { 667 int node, tmp[2]; 668 const char *path; 669 670 ft_cpu_setup(blob, bd); 671 672 node = fdt_path_offset(blob, "/aliases"); 673 tmp[0] = 0; 674 if (node >= 0) { 675 #ifdef CONFIG_PCI1 676 path = fdt_getprop(blob, node, "pci0", NULL); 677 if (path) { 678 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 679 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 680 } 681 #endif 682 #ifdef CONFIG_PCIE2 683 path = fdt_getprop(blob, node, "pci1", NULL); 684 if (path) { 685 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; 686 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 687 } 688 #endif 689 #ifdef CONFIG_PCIE1 690 path = fdt_getprop(blob, node, "pci2", NULL); 691 if (path) { 692 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 693 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 694 } 695 #endif 696 #ifdef CONFIG_PCIE3 697 path = fdt_getprop(blob, node, "pci3", NULL); 698 if (path) { 699 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; 700 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 701 } 702 #endif 703 } 704 } 705 #endif 706