1 /* 2 * Copyright 2008-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <asm/fsl_serdes.h> 34 #include <spd.h> 35 #include <miiphy.h> 36 #include <libfdt.h> 37 #include <spd_sdram.h> 38 #include <fdt_support.h> 39 #include <tsec.h> 40 #include <netdev.h> 41 #include <sata.h> 42 43 #include "../common/sgmii_riser.h" 44 45 int board_early_init_f (void) 46 { 47 #ifdef CONFIG_MMC 48 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 49 50 setbits_be32(&gur->pmuxcr, 51 (MPC85xx_PMUXCR_SD_DATA | 52 MPC85xx_PMUXCR_SDHC_CD | 53 MPC85xx_PMUXCR_SDHC_WP)); 54 55 #endif 56 return 0; 57 } 58 59 int checkboard (void) 60 { 61 u8 vboot; 62 u8 *pixis_base = (u8 *)PIXIS_BASE; 63 64 puts("Board: MPC8536DS "); 65 #ifdef CONFIG_PHYS_64BIT 66 puts("(36-bit addrmap) "); 67 #endif 68 69 printf ("Sys ID: 0x%02x, " 70 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 71 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 72 in_8(pixis_base + PIXIS_PVER)); 73 74 vboot = in_8(pixis_base + PIXIS_VBOOT); 75 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 76 case PIXIS_VBOOT_LBMAP_NOR0: 77 puts ("vBank: 0\n"); 78 break; 79 case PIXIS_VBOOT_LBMAP_NOR1: 80 puts ("vBank: 1\n"); 81 break; 82 case PIXIS_VBOOT_LBMAP_NOR2: 83 puts ("vBank: 2\n"); 84 break; 85 case PIXIS_VBOOT_LBMAP_NOR3: 86 puts ("vBank: 3\n"); 87 break; 88 case PIXIS_VBOOT_LBMAP_PJET: 89 puts ("Promjet\n"); 90 break; 91 case PIXIS_VBOOT_LBMAP_NAND: 92 puts ("NAND\n"); 93 break; 94 } 95 96 return 0; 97 } 98 99 #if !defined(CONFIG_SPD_EEPROM) 100 /* 101 * Fixed sdram init -- doesn't use serial presence detect. 102 */ 103 104 phys_size_t fixed_sdram (void) 105 { 106 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 107 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 108 uint d_init; 109 110 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 111 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 112 113 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 114 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 115 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 116 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 117 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 118 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 119 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 120 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 121 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 122 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 123 124 #if defined (CONFIG_DDR_ECC) 125 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 126 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 127 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 128 #endif 129 asm("sync;isync"); 130 131 udelay(500); 132 133 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 134 135 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 136 d_init = 1; 137 debug("DDR - 1st controller: memory initializing\n"); 138 /* 139 * Poll until memory is initialized. 140 * 512 Meg at 400 might hit this 200 times or so. 141 */ 142 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 143 udelay(1000); 144 } 145 debug("DDR: memory initialized\n\n"); 146 asm("sync; isync"); 147 udelay(500); 148 #endif 149 150 return 512 * 1024 * 1024; 151 } 152 153 #endif 154 155 #ifdef CONFIG_PCI1 156 static struct pci_controller pci1_hose; 157 #endif 158 159 #ifdef CONFIG_PCI 160 void pci_init_board(void) 161 { 162 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 163 struct fsl_pci_info pci_info; 164 u32 devdisr, pordevsr; 165 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 166 int first_free_busno; 167 168 first_free_busno = fsl_pcie_init_board(0); 169 170 #ifdef CONFIG_PCI1 171 devdisr = in_be32(&gur->devdisr); 172 pordevsr = in_be32(&gur->pordevsr); 173 porpllsr = in_be32(&gur->porpllsr); 174 175 pci_speed = 66666000; 176 pci_32 = 1; 177 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 178 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 179 180 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 181 SET_STD_PCI_INFO(pci_info, 1); 182 set_next_law(pci_info.mem_phys, 183 law_size_bits(pci_info.mem_size), pci_info.law); 184 set_next_law(pci_info.io_phys, 185 law_size_bits(pci_info.io_size), pci_info.law); 186 187 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 188 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 189 (pci_32) ? 32 : 64, 190 (pci_speed == 33333000) ? "33" : 191 (pci_speed == 66666000) ? "66" : "unknown", 192 pci_clk_sel ? "sync" : "async", 193 pci_agent ? "agent" : "host", 194 pci_arb ? "arbiter" : "external-arbiter", 195 pci_info.regs); 196 197 first_free_busno = fsl_pci_init_port(&pci_info, 198 &pci1_hose, first_free_busno); 199 } else { 200 printf("PCI: disabled\n"); 201 } 202 203 puts("\n"); 204 #else 205 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 206 #endif 207 } 208 #endif 209 210 int board_early_init_r(void) 211 { 212 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 213 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 214 215 /* 216 * Remap Boot flash + PROMJET region to caching-inhibited 217 * so that flash can be erased properly. 218 */ 219 220 /* Flush d-cache and invalidate i-cache of any FLASH data */ 221 flush_dcache(); 222 invalidate_icache(); 223 224 /* invalidate existing TLB entry for flash + promjet */ 225 disable_tlb(flash_esel); 226 227 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 228 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 229 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 230 231 return 0; 232 } 233 234 int board_eth_init(bd_t *bis) 235 { 236 #ifdef CONFIG_TSEC_ENET 237 struct tsec_info_struct tsec_info[2]; 238 int num = 0; 239 240 #ifdef CONFIG_TSEC1 241 SET_STD_TSEC_INFO(tsec_info[num], 1); 242 if (is_serdes_configured(SGMII_TSEC1)) { 243 puts("eTSEC1 is in sgmii mode.\n"); 244 tsec_info[num].phyaddr = 0; 245 tsec_info[num].flags |= TSEC_SGMII; 246 } 247 num++; 248 #endif 249 #ifdef CONFIG_TSEC3 250 SET_STD_TSEC_INFO(tsec_info[num], 3); 251 if (is_serdes_configured(SGMII_TSEC3)) { 252 puts("eTSEC3 is in sgmii mode.\n"); 253 tsec_info[num].phyaddr = 1; 254 tsec_info[num].flags |= TSEC_SGMII; 255 } 256 num++; 257 #endif 258 259 if (!num) { 260 printf("No TSECs initialized\n"); 261 return 0; 262 } 263 264 #ifdef CONFIG_FSL_SGMII_RISER 265 if (is_serdes_configured(SGMII_TSEC1) || 266 is_serdes_configured(SGMII_TSEC3)) { 267 fsl_sgmii_riser_init(tsec_info, num); 268 } 269 #endif 270 271 tsec_eth_init(bis, tsec_info, num); 272 #endif 273 return pci_eth_init(bis); 274 } 275 276 #if defined(CONFIG_OF_BOARD_SETUP) 277 void ft_board_setup(void *blob, bd_t *bd) 278 { 279 ft_cpu_setup(blob, bd); 280 281 FT_FSL_PCI_SETUP; 282 283 #ifdef CONFIG_FSL_SGMII_RISER 284 fsl_sgmii_riser_fdt_fixup(blob); 285 #endif 286 } 287 #endif 288