1 /* 2 * Copyright 2008 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <spd_sdram.h> 37 #include <fdt_support.h> 38 #include <tsec.h> 39 #include <netdev.h> 40 #include <sata.h> 41 42 #include "../common/pixis.h" 43 #include "../common/sgmii_riser.h" 44 45 phys_size_t fixed_sdram(void); 46 47 int board_early_init_f (void) 48 { 49 #ifdef CONFIG_MMC 50 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 51 52 setbits_be32(&gur->pmuxcr, 53 (MPC85xx_PMUXCR_SD_DATA | 54 MPC85xx_PMUXCR_SDHC_CD | 55 MPC85xx_PMUXCR_SDHC_WP)); 56 57 #endif 58 return 0; 59 } 60 61 int checkboard (void) 62 { 63 u8 vboot; 64 u8 *pixis_base = (u8 *)PIXIS_BASE; 65 66 puts("Board: MPC8536DS "); 67 #ifdef CONFIG_PHYS_64BIT 68 puts("(36-bit addrmap) "); 69 #endif 70 71 printf ("Sys ID: 0x%02x, " 72 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 73 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 74 in_8(pixis_base + PIXIS_PVER)); 75 76 vboot = in_8(pixis_base + PIXIS_VBOOT); 77 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 78 case PIXIS_VBOOT_LBMAP_NOR0: 79 puts ("vBank: 0\n"); 80 break; 81 case PIXIS_VBOOT_LBMAP_NOR1: 82 puts ("vBank: 1\n"); 83 break; 84 case PIXIS_VBOOT_LBMAP_NOR2: 85 puts ("vBank: 2\n"); 86 break; 87 case PIXIS_VBOOT_LBMAP_NOR3: 88 puts ("vBank: 3\n"); 89 break; 90 case PIXIS_VBOOT_LBMAP_PJET: 91 puts ("Promjet\n"); 92 break; 93 case PIXIS_VBOOT_LBMAP_NAND: 94 puts ("NAND\n"); 95 break; 96 } 97 98 return 0; 99 } 100 101 phys_size_t 102 initdram(int board_type) 103 { 104 phys_size_t dram_size = 0; 105 106 puts("Initializing...."); 107 108 #ifdef CONFIG_SPD_EEPROM 109 dram_size = fsl_ddr_sdram(); 110 #else 111 dram_size = fixed_sdram(); 112 #endif 113 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 114 dram_size *= 0x100000; 115 116 puts(" DDR: "); 117 return dram_size; 118 } 119 120 #if !defined(CONFIG_SPD_EEPROM) 121 /* 122 * Fixed sdram init -- doesn't use serial presence detect. 123 */ 124 125 phys_size_t fixed_sdram (void) 126 { 127 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 128 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 129 uint d_init; 130 131 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 132 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 133 134 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 135 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 136 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 137 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 138 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 139 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 140 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 141 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 142 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 143 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 144 145 #if defined (CONFIG_DDR_ECC) 146 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 147 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 148 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 149 #endif 150 asm("sync;isync"); 151 152 udelay(500); 153 154 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 155 156 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 157 d_init = 1; 158 debug("DDR - 1st controller: memory initializing\n"); 159 /* 160 * Poll until memory is initialized. 161 * 512 Meg at 400 might hit this 200 times or so. 162 */ 163 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 164 udelay(1000); 165 } 166 debug("DDR: memory initialized\n\n"); 167 asm("sync; isync"); 168 udelay(500); 169 #endif 170 171 return 512 * 1024 * 1024; 172 } 173 174 #endif 175 176 #ifdef CONFIG_PCI1 177 static struct pci_controller pci1_hose; 178 #endif 179 180 #ifdef CONFIG_PCIE1 181 static struct pci_controller pcie1_hose; 182 #endif 183 184 #ifdef CONFIG_PCIE2 185 static struct pci_controller pcie2_hose; 186 #endif 187 188 #ifdef CONFIG_PCIE3 189 static struct pci_controller pcie3_hose; 190 #endif 191 192 int first_free_busno=0; 193 194 void 195 pci_init_board(void) 196 { 197 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 198 uint devdisr = gur->devdisr; 199 uint sdrs2_io_sel = 200 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 201 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 202 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 203 204 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ 205 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); 206 207 if (sdrs2_io_sel == 7) 208 printf(" Serdes2 disalbed\n"); 209 else if (sdrs2_io_sel == 4) { 210 printf(" eTSEC1 is in sgmii mode.\n"); 211 printf(" eTSEC3 is in sgmii mode.\n"); 212 } else if (sdrs2_io_sel == 6) 213 printf(" eTSEC1 is in sgmii mode.\n"); 214 215 #ifdef CONFIG_PCIE3 216 { 217 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 218 struct pci_controller *hose = &pcie3_hose; 219 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); 220 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); 221 struct pci_region *r = hose->regions; 222 223 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 224 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", 225 pcie_ep ? "End Point" : "Root Complex", 226 (uint)pci); 227 if (pci->pme_msg_det) { 228 pci->pme_msg_det = 0xffffffff; 229 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 230 } 231 printf ("\n"); 232 233 /* outbound memory */ 234 pci_set_region(r++, 235 CONFIG_SYS_PCIE3_MEM_BUS, 236 CONFIG_SYS_PCIE3_MEM_PHYS, 237 CONFIG_SYS_PCIE3_MEM_SIZE, 238 PCI_REGION_MEM); 239 240 /* outbound io */ 241 pci_set_region(r++, 242 CONFIG_SYS_PCIE3_IO_BUS, 243 CONFIG_SYS_PCIE3_IO_PHYS, 244 CONFIG_SYS_PCIE3_IO_SIZE, 245 PCI_REGION_IO); 246 247 hose->region_count = r - hose->regions; 248 249 hose->first_busno=first_free_busno; 250 251 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 252 253 first_free_busno=hose->last_busno+1; 254 printf (" PCIE3 on bus %02x - %02x\n", 255 hose->first_busno,hose->last_busno); 256 } else { 257 printf (" PCIE3: disabled\n"); 258 } 259 } 260 #else 261 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 262 #endif 263 264 #ifdef CONFIG_PCIE1 265 { 266 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 267 struct pci_controller *hose = &pcie1_hose; 268 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); 269 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 270 struct pci_region *r = hose->regions; 271 272 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 273 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", 274 pcie_ep ? "End Point" : "Root Complex", 275 (uint)pci); 276 if (pci->pme_msg_det) { 277 pci->pme_msg_det = 0xffffffff; 278 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 279 } 280 printf ("\n"); 281 282 /* outbound memory */ 283 pci_set_region(r++, 284 CONFIG_SYS_PCIE1_MEM_BUS, 285 CONFIG_SYS_PCIE1_MEM_PHYS, 286 CONFIG_SYS_PCIE1_MEM_SIZE, 287 PCI_REGION_MEM); 288 289 /* outbound io */ 290 pci_set_region(r++, 291 CONFIG_SYS_PCIE1_IO_BUS, 292 CONFIG_SYS_PCIE1_IO_PHYS, 293 CONFIG_SYS_PCIE1_IO_SIZE, 294 PCI_REGION_IO); 295 296 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 297 /* outbound memory */ 298 pci_set_region(r++, 299 CONFIG_SYS_PCIE1_MEM_BUS2, 300 CONFIG_SYS_PCIE1_MEM_PHYS2, 301 CONFIG_SYS_PCIE1_MEM_SIZE2, 302 PCI_REGION_MEM); 303 #endif 304 hose->region_count = r - hose->regions; 305 hose->first_busno=first_free_busno; 306 307 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 308 309 first_free_busno=hose->last_busno+1; 310 printf(" PCIE1 on bus %02x - %02x\n", 311 hose->first_busno,hose->last_busno); 312 313 } else { 314 printf (" PCIE1: disabled\n"); 315 } 316 } 317 #else 318 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 319 #endif 320 321 #ifdef CONFIG_PCIE2 322 { 323 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 324 struct pci_controller *hose = &pcie2_hose; 325 int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); 326 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 327 struct pci_region *r = hose->regions; 328 329 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 330 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", 331 pcie_ep ? "End Point" : "Root Complex", 332 (uint)pci); 333 if (pci->pme_msg_det) { 334 pci->pme_msg_det = 0xffffffff; 335 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 336 } 337 printf ("\n"); 338 339 /* outbound memory */ 340 pci_set_region(r++, 341 CONFIG_SYS_PCIE2_MEM_BUS, 342 CONFIG_SYS_PCIE2_MEM_PHYS, 343 CONFIG_SYS_PCIE2_MEM_SIZE, 344 PCI_REGION_MEM); 345 346 /* outbound io */ 347 pci_set_region(r++, 348 CONFIG_SYS_PCIE2_IO_BUS, 349 CONFIG_SYS_PCIE2_IO_PHYS, 350 CONFIG_SYS_PCIE2_IO_SIZE, 351 PCI_REGION_IO); 352 353 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 354 /* outbound memory */ 355 pci_set_region(r++, 356 CONFIG_SYS_PCIE2_MEM_BUS2, 357 CONFIG_SYS_PCIE2_MEM_PHYS2, 358 CONFIG_SYS_PCIE2_MEM_SIZE2, 359 PCI_REGION_MEM); 360 #endif 361 hose->region_count = r - hose->regions; 362 hose->first_busno=first_free_busno; 363 364 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 365 first_free_busno=hose->last_busno+1; 366 printf (" PCIE2 on bus %02x - %02x\n", 367 hose->first_busno,hose->last_busno); 368 369 } else { 370 printf (" PCIE2: disabled\n"); 371 } 372 } 373 #else 374 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 375 #endif 376 377 #ifdef CONFIG_PCI1 378 { 379 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 380 struct pci_controller *hose = &pci1_hose; 381 struct pci_region *r = hose->regions; 382 383 uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent); 384 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 385 uint pci_32 = 1; 386 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 387 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 388 389 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 390 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 391 (pci_32) ? 32 : 64, 392 (pci_speed == 33333000) ? "33" : 393 (pci_speed == 66666000) ? "66" : "unknown", 394 pci_clk_sel ? "sync" : "async", 395 pci_agent ? "agent" : "host", 396 pci_arb ? "arbiter" : "external-arbiter", 397 (uint)pci 398 ); 399 400 /* outbound memory */ 401 pci_set_region(r++, 402 CONFIG_SYS_PCI1_MEM_BUS, 403 CONFIG_SYS_PCI1_MEM_PHYS, 404 CONFIG_SYS_PCI1_MEM_SIZE, 405 PCI_REGION_MEM); 406 407 /* outbound io */ 408 pci_set_region(r++, 409 CONFIG_SYS_PCI1_IO_BUS, 410 CONFIG_SYS_PCI1_IO_PHYS, 411 CONFIG_SYS_PCI1_IO_SIZE, 412 PCI_REGION_IO); 413 414 #ifdef CONFIG_SYS_PCI1_MEM_BUS2 415 /* outbound memory */ 416 pci_set_region(r++, 417 CONFIG_SYS_PCI1_MEM_BUS2, 418 CONFIG_SYS_PCI1_MEM_PHYS2, 419 CONFIG_SYS_PCI1_MEM_SIZE2, 420 PCI_REGION_MEM); 421 #endif 422 hose->region_count = r - hose->regions; 423 hose->first_busno=first_free_busno; 424 425 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 426 first_free_busno=hose->last_busno+1; 427 printf ("PCI on bus %02x - %02x\n", 428 hose->first_busno,hose->last_busno); 429 } else { 430 printf (" PCI: disabled\n"); 431 } 432 } 433 #else 434 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 435 #endif 436 } 437 438 int board_early_init_r(void) 439 { 440 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 441 const u8 flash_esel = 1; 442 443 /* 444 * Remap Boot flash + PROMJET region to caching-inhibited 445 * so that flash can be erased properly. 446 */ 447 448 /* Flush d-cache and invalidate i-cache of any FLASH data */ 449 flush_dcache(); 450 invalidate_icache(); 451 452 /* invalidate existing TLB entry for flash + promjet */ 453 disable_tlb(flash_esel); 454 455 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 456 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 457 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 458 459 return 0; 460 } 461 462 #ifdef CONFIG_GET_CLK_FROM_ICS307 463 /* decode S[0-2] to Output Divider (OD) */ 464 static unsigned char 465 ics307_S_to_OD[] = { 466 10, 2, 8, 4, 5, 7, 3, 6 467 }; 468 469 /* Calculate frequency being generated by ICS307-02 clock chip based upon 470 * the control bytes being programmed into it. */ 471 /* XXX: This function should probably go into a common library */ 472 static unsigned long 473 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 474 { 475 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 476 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 477 unsigned long RDW = cw2 & 0x7F; 478 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 479 unsigned long freq; 480 481 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 482 483 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 484 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 485 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 486 * 487 * R6:R0 = Reference Divider Word (RDW) 488 * V8:V0 = VCO Divider Word (VDW) 489 * S2:S0 = Output Divider Select (OD) 490 * F1:F0 = Function of CLK2 Output 491 * TTL = duty cycle 492 * C1:C0 = internal load capacitance for cyrstal 493 */ 494 495 /* Adding 1 to get a "nicely" rounded number, but this needs 496 * more tweaking to get a "properly" rounded number. */ 497 498 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 499 500 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 501 freq); 502 return freq; 503 } 504 505 unsigned long 506 get_board_sys_clk(ulong dummy) 507 { 508 u8 *pixis_base = (u8 *)PIXIS_BASE; 509 510 return ics307_clk_freq ( 511 in_8(pixis_base + PIXIS_VSYSCLK0), 512 in_8(pixis_base + PIXIS_VSYSCLK1), 513 in_8(pixis_base + PIXIS_VSYSCLK2) 514 ); 515 } 516 517 unsigned long 518 get_board_ddr_clk(ulong dummy) 519 { 520 u8 *pixis_base = (u8 *)PIXIS_BASE; 521 522 return ics307_clk_freq ( 523 in_8(pixis_base + PIXIS_VDDRCLK0), 524 in_8(pixis_base + PIXIS_VDDRCLK1), 525 in_8(pixis_base + PIXIS_VDDRCLK2) 526 ); 527 } 528 #else 529 unsigned long 530 get_board_sys_clk(ulong dummy) 531 { 532 u8 i; 533 ulong val = 0; 534 u8 *pixis_base = (u8 *)PIXIS_BASE; 535 536 i = in_8(pixis_base + PIXIS_SPD); 537 i &= 0x07; 538 539 switch (i) { 540 case 0: 541 val = 33333333; 542 break; 543 case 1: 544 val = 40000000; 545 break; 546 case 2: 547 val = 50000000; 548 break; 549 case 3: 550 val = 66666666; 551 break; 552 case 4: 553 val = 83333333; 554 break; 555 case 5: 556 val = 100000000; 557 break; 558 case 6: 559 val = 133333333; 560 break; 561 case 7: 562 val = 166666666; 563 break; 564 } 565 566 return val; 567 } 568 569 unsigned long 570 get_board_ddr_clk(ulong dummy) 571 { 572 u8 i; 573 ulong val = 0; 574 u8 *pixis_base = (u8 *)PIXIS_BASE; 575 576 i = in_8(pixis_base + PIXIS_SPD); 577 i &= 0x38; 578 i >>= 3; 579 580 switch (i) { 581 case 0: 582 val = 33333333; 583 break; 584 case 1: 585 val = 40000000; 586 break; 587 case 2: 588 val = 50000000; 589 break; 590 case 3: 591 val = 66666666; 592 break; 593 case 4: 594 val = 83333333; 595 break; 596 case 5: 597 val = 100000000; 598 break; 599 case 6: 600 val = 133333333; 601 break; 602 case 7: 603 val = 166666666; 604 break; 605 } 606 return val; 607 } 608 #endif 609 610 int sata_initialize(void) 611 { 612 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 613 uint sdrs2_io_sel = 614 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 615 if (sdrs2_io_sel & 0x04) 616 return 1; 617 618 return __sata_initialize(); 619 } 620 621 int board_eth_init(bd_t *bis) 622 { 623 #ifdef CONFIG_TSEC_ENET 624 struct tsec_info_struct tsec_info[2]; 625 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 626 int num = 0; 627 uint sdrs2_io_sel = 628 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 629 630 #ifdef CONFIG_TSEC1 631 SET_STD_TSEC_INFO(tsec_info[num], 1); 632 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { 633 tsec_info[num].phyaddr = 0; 634 tsec_info[num].flags |= TSEC_SGMII; 635 } 636 num++; 637 #endif 638 #ifdef CONFIG_TSEC3 639 SET_STD_TSEC_INFO(tsec_info[num], 3); 640 if (sdrs2_io_sel == 4) { 641 tsec_info[num].phyaddr = 1; 642 tsec_info[num].flags |= TSEC_SGMII; 643 } 644 num++; 645 #endif 646 647 if (!num) { 648 printf("No TSECs initialized\n"); 649 return 0; 650 } 651 652 #ifdef CONFIG_FSL_SGMII_RISER 653 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) 654 fsl_sgmii_riser_init(tsec_info, num); 655 #endif 656 657 tsec_eth_init(bis, tsec_info, num); 658 #endif 659 return pci_eth_init(bis); 660 } 661 662 #if defined(CONFIG_OF_BOARD_SETUP) 663 void ft_board_setup(void *blob, bd_t *bd) 664 { 665 ft_cpu_setup(blob, bd); 666 667 #ifdef CONFIG_PCI1 668 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 669 #endif 670 #ifdef CONFIG_PCIE2 671 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 672 #endif 673 #ifdef CONFIG_PCIE2 674 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 675 #endif 676 #ifdef CONFIG_PCIE1 677 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); 678 #endif 679 #ifdef CONFIG_FSL_SGMII_RISER 680 fsl_sgmii_riser_fdt_fixup(blob); 681 #endif 682 } 683 #endif 684