1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2008-2012 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <command.h> 8 #include <pci.h> 9 #include <asm/processor.h> 10 #include <asm/mmu.h> 11 #include <asm/cache.h> 12 #include <asm/immap_85xx.h> 13 #include <asm/fsl_pci.h> 14 #include <fsl_ddr_sdram.h> 15 #include <asm/io.h> 16 #include <asm/fsl_serdes.h> 17 #include <spd.h> 18 #include <miiphy.h> 19 #include <linux/libfdt.h> 20 #include <spd_sdram.h> 21 #include <fdt_support.h> 22 #include <fsl_mdio.h> 23 #include <tsec.h> 24 #include <netdev.h> 25 #include <sata.h> 26 27 #include "../common/sgmii_riser.h" 28 29 int board_early_init_f (void) 30 { 31 #ifdef CONFIG_MMC 32 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 33 34 setbits_be32(&gur->pmuxcr, 35 (MPC85xx_PMUXCR_SDHC_CD | 36 MPC85xx_PMUXCR_SDHC_WP)); 37 38 /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118, 39 * however, this erratum only applies to MPC8536 Rev1.0. 40 * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/ 41 if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) && 42 (SVR_MIN(get_svr()) >= 0x1)) 43 || (SVR_MAJ(get_svr() & 0x7) > 0x1)) 44 setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV); 45 #endif 46 return 0; 47 } 48 49 int checkboard (void) 50 { 51 u8 vboot; 52 u8 *pixis_base = (u8 *)PIXIS_BASE; 53 54 printf("Board: MPC8536DS Sys ID: 0x%02x, " 55 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 56 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 57 in_8(pixis_base + PIXIS_PVER)); 58 59 vboot = in_8(pixis_base + PIXIS_VBOOT); 60 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 61 case PIXIS_VBOOT_LBMAP_NOR0: 62 puts ("vBank: 0\n"); 63 break; 64 case PIXIS_VBOOT_LBMAP_NOR1: 65 puts ("vBank: 1\n"); 66 break; 67 case PIXIS_VBOOT_LBMAP_NOR2: 68 puts ("vBank: 2\n"); 69 break; 70 case PIXIS_VBOOT_LBMAP_NOR3: 71 puts ("vBank: 3\n"); 72 break; 73 case PIXIS_VBOOT_LBMAP_PJET: 74 puts ("Promjet\n"); 75 break; 76 case PIXIS_VBOOT_LBMAP_NAND: 77 puts ("NAND\n"); 78 break; 79 } 80 81 return 0; 82 } 83 84 #if !defined(CONFIG_SPD_EEPROM) 85 /* 86 * Fixed sdram init -- doesn't use serial presence detect. 87 */ 88 89 phys_size_t fixed_sdram (void) 90 { 91 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 92 struct ccsr_ddr __iomem *ddr = &immap->im_ddr; 93 uint d_init; 94 95 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 96 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 97 98 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 99 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 100 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 101 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 102 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 103 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 104 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 105 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 106 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 107 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 108 109 #if defined (CONFIG_DDR_ECC) 110 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 111 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 112 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 113 #endif 114 asm("sync;isync"); 115 116 udelay(500); 117 118 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 119 120 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 121 d_init = 1; 122 debug("DDR - 1st controller: memory initializing\n"); 123 /* 124 * Poll until memory is initialized. 125 * 512 Meg at 400 might hit this 200 times or so. 126 */ 127 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 128 udelay(1000); 129 } 130 debug("DDR: memory initialized\n\n"); 131 asm("sync; isync"); 132 udelay(500); 133 #endif 134 135 return 512 * 1024 * 1024; 136 } 137 138 #endif 139 140 #ifdef CONFIG_PCI1 141 static struct pci_controller pci1_hose; 142 #endif 143 144 #ifdef CONFIG_PCI 145 void pci_init_board(void) 146 { 147 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 148 struct fsl_pci_info pci_info; 149 u32 devdisr, pordevsr; 150 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 151 int first_free_busno; 152 153 first_free_busno = fsl_pcie_init_board(0); 154 155 #ifdef CONFIG_PCI1 156 devdisr = in_be32(&gur->devdisr); 157 pordevsr = in_be32(&gur->pordevsr); 158 porpllsr = in_be32(&gur->porpllsr); 159 160 pci_speed = 66666000; 161 pci_32 = 1; 162 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 163 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 164 165 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 166 SET_STD_PCI_INFO(pci_info, 1); 167 set_next_law(pci_info.mem_phys, 168 law_size_bits(pci_info.mem_size), pci_info.law); 169 set_next_law(pci_info.io_phys, 170 law_size_bits(pci_info.io_size), pci_info.law); 171 172 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 173 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 174 (pci_32) ? 32 : 64, 175 (pci_speed == 33333000) ? "33" : 176 (pci_speed == 66666000) ? "66" : "unknown", 177 pci_clk_sel ? "sync" : "async", 178 pci_agent ? "agent" : "host", 179 pci_arb ? "arbiter" : "external-arbiter", 180 pci_info.regs); 181 182 first_free_busno = fsl_pci_init_port(&pci_info, 183 &pci1_hose, first_free_busno); 184 } else { 185 printf("PCI: disabled\n"); 186 } 187 188 puts("\n"); 189 #else 190 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 191 #endif 192 } 193 #endif 194 195 int board_early_init_r(void) 196 { 197 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 198 int flash_esel = find_tlb_idx((void *)flashbase, 1); 199 200 /* 201 * Remap Boot flash + PROMJET region to caching-inhibited 202 * so that flash can be erased properly. 203 */ 204 205 /* Flush d-cache and invalidate i-cache of any FLASH data */ 206 flush_dcache(); 207 invalidate_icache(); 208 209 if (flash_esel == -1) { 210 /* very unlikely unless something is messed up */ 211 puts("Error: Could not find TLB for FLASH BASE\n"); 212 flash_esel = 1; /* give our best effort to continue */ 213 } else { 214 /* invalidate existing TLB entry for flash + promjet */ 215 disable_tlb(flash_esel); 216 } 217 218 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 219 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 220 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 221 222 return 0; 223 } 224 225 int board_eth_init(bd_t *bis) 226 { 227 #ifdef CONFIG_TSEC_ENET 228 struct fsl_pq_mdio_info mdio_info; 229 struct tsec_info_struct tsec_info[2]; 230 int num = 0; 231 232 #ifdef CONFIG_TSEC1 233 SET_STD_TSEC_INFO(tsec_info[num], 1); 234 if (is_serdes_configured(SGMII_TSEC1)) { 235 puts("eTSEC1 is in sgmii mode.\n"); 236 tsec_info[num].phyaddr = 0; 237 tsec_info[num].flags |= TSEC_SGMII; 238 } 239 num++; 240 #endif 241 #ifdef CONFIG_TSEC3 242 SET_STD_TSEC_INFO(tsec_info[num], 3); 243 if (is_serdes_configured(SGMII_TSEC3)) { 244 puts("eTSEC3 is in sgmii mode.\n"); 245 tsec_info[num].phyaddr = 1; 246 tsec_info[num].flags |= TSEC_SGMII; 247 } 248 num++; 249 #endif 250 251 if (!num) { 252 printf("No TSECs initialized\n"); 253 return 0; 254 } 255 256 #ifdef CONFIG_FSL_SGMII_RISER 257 if (is_serdes_configured(SGMII_TSEC1) || 258 is_serdes_configured(SGMII_TSEC3)) { 259 fsl_sgmii_riser_init(tsec_info, num); 260 } 261 #endif 262 263 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 264 mdio_info.name = DEFAULT_MII_NAME; 265 fsl_pq_mdio_init(bis, &mdio_info); 266 267 tsec_eth_init(bis, tsec_info, num); 268 #endif 269 return pci_eth_init(bis); 270 } 271 272 #if defined(CONFIG_OF_BOARD_SETUP) 273 int ft_board_setup(void *blob, bd_t *bd) 274 { 275 ft_cpu_setup(blob, bd); 276 277 FT_FSL_PCI_SETUP; 278 279 #ifdef CONFIG_FSL_SGMII_RISER 280 fsl_sgmii_riser_fdt_fixup(blob); 281 #endif 282 283 #ifdef CONFIG_HAS_FSL_MPH_USB 284 fsl_fdt_fixup_dr_usb(blob, bd); 285 #endif 286 287 return 0; 288 } 289 #endif 290