1 /* 2 * Copyright 2008 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/immap_fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <spd_sdram.h> 37 #include <fdt_support.h> 38 #include <tsec.h> 39 #include <netdev.h> 40 41 #include "../common/pixis.h" 42 #include "../common/sgmii_riser.h" 43 44 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 45 extern void ddr_enable_ecc(unsigned int dram_size); 46 #endif 47 48 phys_size_t fixed_sdram(void); 49 50 int checkboard (void) 51 { 52 printf ("Board: MPC8536DS, System ID: 0x%02x, " 53 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 54 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 55 in8(PIXIS_BASE + PIXIS_PVER)); 56 return 0; 57 } 58 59 phys_size_t 60 initdram(int board_type) 61 { 62 phys_size_t dram_size = 0; 63 64 puts("Initializing...."); 65 66 #ifdef CONFIG_SPD_EEPROM 67 dram_size = fsl_ddr_sdram(); 68 69 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 70 71 dram_size *= 0x100000; 72 #else 73 dram_size = fixed_sdram(); 74 #endif 75 76 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 77 /* 78 * Initialize and enable DDR ECC. 79 */ 80 ddr_enable_ecc(dram_size); 81 #endif 82 puts(" DDR: "); 83 return dram_size; 84 } 85 86 #if !defined(CONFIG_SPD_EEPROM) 87 /* 88 * Fixed sdram init -- doesn't use serial presence detect. 89 */ 90 91 phys_size_t fixed_sdram (void) 92 { 93 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 94 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 95 uint d_init; 96 97 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 98 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 99 100 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 101 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 102 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 103 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 104 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 105 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 106 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 107 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 108 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 109 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 110 111 #if defined (CONFIG_DDR_ECC) 112 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 113 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 114 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 115 #endif 116 asm("sync;isync"); 117 118 udelay(500); 119 120 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 121 122 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 123 d_init = 1; 124 debug("DDR - 1st controller: memory initializing\n"); 125 /* 126 * Poll until memory is initialized. 127 * 512 Meg at 400 might hit this 200 times or so. 128 */ 129 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 130 udelay(1000); 131 } 132 debug("DDR: memory initialized\n\n"); 133 asm("sync; isync"); 134 udelay(500); 135 #endif 136 137 return 512 * 1024 * 1024; 138 } 139 140 #endif 141 142 #ifdef CONFIG_PCI1 143 static struct pci_controller pci1_hose; 144 #endif 145 146 #ifdef CONFIG_PCIE1 147 static struct pci_controller pcie1_hose; 148 #endif 149 150 #ifdef CONFIG_PCIE2 151 static struct pci_controller pcie2_hose; 152 #endif 153 154 #ifdef CONFIG_PCIE3 155 static struct pci_controller pcie3_hose; 156 #endif 157 158 extern int fsl_pci_setup_inbound_windows(struct pci_region *r); 159 extern void fsl_pci_init(struct pci_controller *hose); 160 161 int first_free_busno=0; 162 163 void 164 pci_init_board(void) 165 { 166 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 167 uint devdisr = gur->devdisr; 168 uint sdrs2_io_sel = 169 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 170 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 171 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 172 173 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ 174 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); 175 176 if (sdrs2_io_sel == 7) 177 printf(" Serdes2 disalbed\n"); 178 else if (sdrs2_io_sel == 4) { 179 printf(" eTSEC1 is in sgmii mode.\n"); 180 printf(" eTSEC3 is in sgmii mode.\n"); 181 } else if (sdrs2_io_sel == 6) 182 printf(" eTSEC1 is in sgmii mode.\n"); 183 184 #ifdef CONFIG_PCIE3 185 { 186 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 187 struct pci_controller *hose = &pcie3_hose; 188 int pcie_ep = (host_agent == 1); 189 int pcie_configured = (io_sel == 7); 190 struct pci_region *r = hose->regions; 191 192 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 193 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", 194 pcie_ep ? "End Point" : "Root Complex", 195 (uint)pci); 196 if (pci->pme_msg_det) { 197 pci->pme_msg_det = 0xffffffff; 198 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 199 } 200 printf ("\n"); 201 202 /* inbound */ 203 r += fsl_pci_setup_inbound_windows(r); 204 205 /* outbound memory */ 206 pci_set_region(r++, 207 CONFIG_SYS_PCIE3_MEM_BASE, 208 CONFIG_SYS_PCIE3_MEM_PHYS, 209 CONFIG_SYS_PCIE3_MEM_SIZE, 210 PCI_REGION_MEM); 211 212 /* outbound io */ 213 pci_set_region(r++, 214 CONFIG_SYS_PCIE3_IO_BASE, 215 CONFIG_SYS_PCIE3_IO_PHYS, 216 CONFIG_SYS_PCIE3_IO_SIZE, 217 PCI_REGION_IO); 218 219 hose->region_count = r - hose->regions; 220 221 hose->first_busno=first_free_busno; 222 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 223 224 fsl_pci_init(hose); 225 226 first_free_busno=hose->last_busno+1; 227 printf (" PCIE3 on bus %02x - %02x\n", 228 hose->first_busno,hose->last_busno); 229 } else { 230 printf (" PCIE3: disabled\n"); 231 } 232 233 } 234 #else 235 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 236 #endif 237 238 #ifdef CONFIG_PCIE1 239 { 240 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 241 struct pci_controller *hose = &pcie1_hose; 242 int pcie_ep = (host_agent == 5); 243 int pcie_configured = (io_sel == 2 || io_sel == 3 244 || io_sel == 5 || io_sel == 7); 245 struct pci_region *r = hose->regions; 246 247 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 248 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", 249 pcie_ep ? "End Point" : "Root Complex", 250 (uint)pci); 251 if (pci->pme_msg_det) { 252 pci->pme_msg_det = 0xffffffff; 253 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 254 } 255 printf ("\n"); 256 257 /* inbound */ 258 r += fsl_pci_setup_inbound_windows(r); 259 260 /* outbound memory */ 261 pci_set_region(r++, 262 CONFIG_SYS_PCIE1_MEM_BASE, 263 CONFIG_SYS_PCIE1_MEM_PHYS, 264 CONFIG_SYS_PCIE1_MEM_SIZE, 265 PCI_REGION_MEM); 266 267 /* outbound io */ 268 pci_set_region(r++, 269 CONFIG_SYS_PCIE1_IO_BASE, 270 CONFIG_SYS_PCIE1_IO_PHYS, 271 CONFIG_SYS_PCIE1_IO_SIZE, 272 PCI_REGION_IO); 273 274 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2 275 /* outbound memory */ 276 pci_set_region(r++, 277 CONFIG_SYS_PCIE1_MEM_BASE2, 278 CONFIG_SYS_PCIE1_MEM_PHYS2, 279 CONFIG_SYS_PCIE1_MEM_SIZE2, 280 PCI_REGION_MEM); 281 #endif 282 hose->region_count = r - hose->regions; 283 hose->first_busno=first_free_busno; 284 285 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 286 287 fsl_pci_init(hose); 288 289 first_free_busno=hose->last_busno+1; 290 printf(" PCIE1 on bus %02x - %02x\n", 291 hose->first_busno,hose->last_busno); 292 293 } else { 294 printf (" PCIE1: disabled\n"); 295 } 296 297 } 298 #else 299 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 300 #endif 301 302 #ifdef CONFIG_PCIE2 303 { 304 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 305 struct pci_controller *hose = &pcie2_hose; 306 int pcie_ep = (host_agent == 3); 307 int pcie_configured = (io_sel == 5 || io_sel == 7); 308 struct pci_region *r = hose->regions; 309 310 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 311 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", 312 pcie_ep ? "End Point" : "Root Complex", 313 (uint)pci); 314 if (pci->pme_msg_det) { 315 pci->pme_msg_det = 0xffffffff; 316 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 317 } 318 printf ("\n"); 319 320 /* inbound */ 321 r += fsl_pci_setup_inbound_windows(r); 322 323 /* outbound memory */ 324 pci_set_region(r++, 325 CONFIG_SYS_PCIE2_MEM_BASE, 326 CONFIG_SYS_PCIE2_MEM_PHYS, 327 CONFIG_SYS_PCIE2_MEM_SIZE, 328 PCI_REGION_MEM); 329 330 /* outbound io */ 331 pci_set_region(r++, 332 CONFIG_SYS_PCIE2_IO_BASE, 333 CONFIG_SYS_PCIE2_IO_PHYS, 334 CONFIG_SYS_PCIE2_IO_SIZE, 335 PCI_REGION_IO); 336 337 #ifdef CONFIG_SYS_PCIE2_MEM_BASE2 338 /* outbound memory */ 339 pci_set_region(r++, 340 CONFIG_SYS_PCIE2_MEM_BASE2, 341 CONFIG_SYS_PCIE2_MEM_PHYS2, 342 CONFIG_SYS_PCIE2_MEM_SIZE2, 343 PCI_REGION_MEM); 344 #endif 345 hose->region_count = r - hose->regions; 346 hose->first_busno=first_free_busno; 347 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 348 349 fsl_pci_init(hose); 350 first_free_busno=hose->last_busno+1; 351 printf (" PCIE2 on bus %02x - %02x\n", 352 hose->first_busno,hose->last_busno); 353 354 } else { 355 printf (" PCIE2: disabled\n"); 356 } 357 358 } 359 #else 360 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 361 #endif 362 363 364 #ifdef CONFIG_PCI1 365 { 366 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 367 struct pci_controller *hose = &pci1_hose; 368 struct pci_region *r = hose->regions; 369 370 uint pci_agent = (host_agent == 6); 371 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 372 uint pci_32 = 1; 373 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 374 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 375 376 377 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 378 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 379 (pci_32) ? 32 : 64, 380 (pci_speed == 33333000) ? "33" : 381 (pci_speed == 66666000) ? "66" : "unknown", 382 pci_clk_sel ? "sync" : "async", 383 pci_agent ? "agent" : "host", 384 pci_arb ? "arbiter" : "external-arbiter", 385 (uint)pci 386 ); 387 388 /* inbound */ 389 r += fsl_pci_setup_inbound_windows(r); 390 391 /* outbound memory */ 392 pci_set_region(r++, 393 CONFIG_SYS_PCI1_MEM_BASE, 394 CONFIG_SYS_PCI1_MEM_PHYS, 395 CONFIG_SYS_PCI1_MEM_SIZE, 396 PCI_REGION_MEM); 397 398 /* outbound io */ 399 pci_set_region(r++, 400 CONFIG_SYS_PCI1_IO_BASE, 401 CONFIG_SYS_PCI1_IO_PHYS, 402 CONFIG_SYS_PCI1_IO_SIZE, 403 PCI_REGION_IO); 404 405 #ifdef CONFIG_SYS_PCI1_MEM_BASE2 406 /* outbound memory */ 407 pci_set_region(r++, 408 CONFIG_SYS_PCI1_MEM_BASE2, 409 CONFIG_SYS_PCI1_MEM_PHYS2, 410 CONFIG_SYS_PCI1_MEM_SIZE2, 411 PCI_REGION_MEM); 412 #endif 413 hose->region_count = r - hose->regions; 414 hose->first_busno=first_free_busno; 415 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 416 417 fsl_pci_init(hose); 418 first_free_busno=hose->last_busno+1; 419 printf ("PCI on bus %02x - %02x\n", 420 hose->first_busno,hose->last_busno); 421 } else { 422 printf (" PCI: disabled\n"); 423 } 424 } 425 #else 426 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 427 #endif 428 } 429 430 431 int board_early_init_r(void) 432 { 433 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 434 const u8 flash_esel = 1; 435 436 /* 437 * Remap Boot flash + PROMJET region to caching-inhibited 438 * so that flash can be erased properly. 439 */ 440 441 /* Flush d-cache and invalidate i-cache of any FLASH data */ 442 flush_dcache(); 443 invalidate_icache(); 444 445 /* invalidate existing TLB entry for flash + promjet */ 446 disable_tlb(flash_esel); 447 448 set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ 449 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 450 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 451 452 return 0; 453 } 454 455 #ifdef CONFIG_GET_CLK_FROM_ICS307 456 /* decode S[0-2] to Output Divider (OD) */ 457 static unsigned char 458 ics307_S_to_OD[] = { 459 10, 2, 8, 4, 5, 7, 3, 6 460 }; 461 462 /* Calculate frequency being generated by ICS307-02 clock chip based upon 463 * the control bytes being programmed into it. */ 464 /* XXX: This function should probably go into a common library */ 465 static unsigned long 466 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 467 { 468 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 469 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 470 unsigned long RDW = cw2 & 0x7F; 471 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 472 unsigned long freq; 473 474 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 475 476 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 477 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 478 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 479 * 480 * R6:R0 = Reference Divider Word (RDW) 481 * V8:V0 = VCO Divider Word (VDW) 482 * S2:S0 = Output Divider Select (OD) 483 * F1:F0 = Function of CLK2 Output 484 * TTL = duty cycle 485 * C1:C0 = internal load capacitance for cyrstal 486 */ 487 488 /* Adding 1 to get a "nicely" rounded number, but this needs 489 * more tweaking to get a "properly" rounded number. */ 490 491 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 492 493 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 494 freq); 495 return freq; 496 } 497 498 unsigned long 499 get_board_sys_clk(ulong dummy) 500 { 501 return ics307_clk_freq ( 502 in8(PIXIS_BASE + PIXIS_VSYSCLK0), 503 in8(PIXIS_BASE + PIXIS_VSYSCLK1), 504 in8(PIXIS_BASE + PIXIS_VSYSCLK2) 505 ); 506 } 507 508 unsigned long 509 get_board_ddr_clk(ulong dummy) 510 { 511 return ics307_clk_freq ( 512 in8(PIXIS_BASE + PIXIS_VDDRCLK0), 513 in8(PIXIS_BASE + PIXIS_VDDRCLK1), 514 in8(PIXIS_BASE + PIXIS_VDDRCLK2) 515 ); 516 } 517 #else 518 unsigned long 519 get_board_sys_clk(ulong dummy) 520 { 521 u8 i; 522 ulong val = 0; 523 524 i = in8(PIXIS_BASE + PIXIS_SPD); 525 i &= 0x07; 526 527 switch (i) { 528 case 0: 529 val = 33333333; 530 break; 531 case 1: 532 val = 40000000; 533 break; 534 case 2: 535 val = 50000000; 536 break; 537 case 3: 538 val = 66666666; 539 break; 540 case 4: 541 val = 83333333; 542 break; 543 case 5: 544 val = 100000000; 545 break; 546 case 6: 547 val = 133333333; 548 break; 549 case 7: 550 val = 166666666; 551 break; 552 } 553 554 return val; 555 } 556 557 unsigned long 558 get_board_ddr_clk(ulong dummy) 559 { 560 u8 i; 561 ulong val = 0; 562 563 i = in8(PIXIS_BASE + PIXIS_SPD); 564 i &= 0x38; 565 i >>= 3; 566 567 switch (i) { 568 case 0: 569 val = 33333333; 570 break; 571 case 1: 572 val = 40000000; 573 break; 574 case 2: 575 val = 50000000; 576 break; 577 case 3: 578 val = 66666666; 579 break; 580 case 4: 581 val = 83333333; 582 break; 583 case 5: 584 val = 100000000; 585 break; 586 case 6: 587 val = 133333333; 588 break; 589 case 7: 590 val = 166666666; 591 break; 592 } 593 return val; 594 } 595 #endif 596 597 int is_sata_supported(void) 598 { 599 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 600 uint sdrs2_io_sel = 601 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 602 if (sdrs2_io_sel & 0x04) 603 return 0; 604 605 return 1; 606 } 607 608 int board_eth_init(bd_t *bis) 609 { 610 #ifdef CONFIG_TSEC_ENET 611 struct tsec_info_struct tsec_info[2]; 612 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 613 int num = 0; 614 uint sdrs2_io_sel = 615 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 616 617 #ifdef CONFIG_TSEC1 618 SET_STD_TSEC_INFO(tsec_info[num], 1); 619 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { 620 tsec_info[num].phyaddr = 0; 621 tsec_info[num].flags |= TSEC_SGMII; 622 } 623 num++; 624 #endif 625 #ifdef CONFIG_TSEC3 626 SET_STD_TSEC_INFO(tsec_info[num], 3); 627 if (sdrs2_io_sel == 4) { 628 tsec_info[num].phyaddr = 1; 629 tsec_info[num].flags |= TSEC_SGMII; 630 } 631 num++; 632 #endif 633 634 if (!num) { 635 printf("No TSECs initialized\n"); 636 return 0; 637 } 638 639 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) 640 fsl_sgmii_riser_init(tsec_info, num); 641 642 tsec_eth_init(bis, tsec_info, num); 643 #endif 644 return pci_eth_init(bis); 645 } 646 647 #if defined(CONFIG_OF_BOARD_SETUP) 648 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, 649 struct pci_controller *hose); 650 651 void ft_board_setup(void *blob, bd_t *bd) 652 { 653 ft_cpu_setup(blob, bd); 654 655 #ifdef CONFIG_PCI1 656 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 657 #endif 658 #ifdef CONFIG_PCIE2 659 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 660 #endif 661 #ifdef CONFIG_PCIE2 662 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 663 #endif 664 #ifdef CONFIG_PCIE1 665 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); 666 #endif 667 } 668 #endif 669