1 /* 2 * Copyright 2008-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <asm/fsl_serdes.h> 34 #include <spd.h> 35 #include <miiphy.h> 36 #include <libfdt.h> 37 #include <spd_sdram.h> 38 #include <fdt_support.h> 39 #include <fsl_mdio.h> 40 #include <tsec.h> 41 #include <netdev.h> 42 #include <sata.h> 43 44 #include "../common/sgmii_riser.h" 45 46 int board_early_init_f (void) 47 { 48 #ifdef CONFIG_MMC 49 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50 51 setbits_be32(&gur->pmuxcr, 52 (MPC85xx_PMUXCR_SD_DATA | 53 MPC85xx_PMUXCR_SDHC_CD | 54 MPC85xx_PMUXCR_SDHC_WP)); 55 56 #endif 57 return 0; 58 } 59 60 int checkboard (void) 61 { 62 u8 vboot; 63 u8 *pixis_base = (u8 *)PIXIS_BASE; 64 65 puts("Board: MPC8536DS "); 66 #ifdef CONFIG_PHYS_64BIT 67 puts("(36-bit addrmap) "); 68 #endif 69 70 printf ("Sys ID: 0x%02x, " 71 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 72 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 73 in_8(pixis_base + PIXIS_PVER)); 74 75 vboot = in_8(pixis_base + PIXIS_VBOOT); 76 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 77 case PIXIS_VBOOT_LBMAP_NOR0: 78 puts ("vBank: 0\n"); 79 break; 80 case PIXIS_VBOOT_LBMAP_NOR1: 81 puts ("vBank: 1\n"); 82 break; 83 case PIXIS_VBOOT_LBMAP_NOR2: 84 puts ("vBank: 2\n"); 85 break; 86 case PIXIS_VBOOT_LBMAP_NOR3: 87 puts ("vBank: 3\n"); 88 break; 89 case PIXIS_VBOOT_LBMAP_PJET: 90 puts ("Promjet\n"); 91 break; 92 case PIXIS_VBOOT_LBMAP_NAND: 93 puts ("NAND\n"); 94 break; 95 } 96 97 return 0; 98 } 99 100 #if !defined(CONFIG_SPD_EEPROM) 101 /* 102 * Fixed sdram init -- doesn't use serial presence detect. 103 */ 104 105 phys_size_t fixed_sdram (void) 106 { 107 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 108 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 109 uint d_init; 110 111 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 112 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 113 114 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 115 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 116 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 117 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 118 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 119 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 120 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 121 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 122 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 123 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 124 125 #if defined (CONFIG_DDR_ECC) 126 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 127 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 128 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 129 #endif 130 asm("sync;isync"); 131 132 udelay(500); 133 134 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 135 136 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 137 d_init = 1; 138 debug("DDR - 1st controller: memory initializing\n"); 139 /* 140 * Poll until memory is initialized. 141 * 512 Meg at 400 might hit this 200 times or so. 142 */ 143 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 144 udelay(1000); 145 } 146 debug("DDR: memory initialized\n\n"); 147 asm("sync; isync"); 148 udelay(500); 149 #endif 150 151 return 512 * 1024 * 1024; 152 } 153 154 #endif 155 156 #ifdef CONFIG_PCI1 157 static struct pci_controller pci1_hose; 158 #endif 159 160 #ifdef CONFIG_PCI 161 void pci_init_board(void) 162 { 163 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 164 struct fsl_pci_info pci_info; 165 u32 devdisr, pordevsr; 166 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 167 int first_free_busno; 168 169 first_free_busno = fsl_pcie_init_board(0); 170 171 #ifdef CONFIG_PCI1 172 devdisr = in_be32(&gur->devdisr); 173 pordevsr = in_be32(&gur->pordevsr); 174 porpllsr = in_be32(&gur->porpllsr); 175 176 pci_speed = 66666000; 177 pci_32 = 1; 178 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 179 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 180 181 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 182 SET_STD_PCI_INFO(pci_info, 1); 183 set_next_law(pci_info.mem_phys, 184 law_size_bits(pci_info.mem_size), pci_info.law); 185 set_next_law(pci_info.io_phys, 186 law_size_bits(pci_info.io_size), pci_info.law); 187 188 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 189 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 190 (pci_32) ? 32 : 64, 191 (pci_speed == 33333000) ? "33" : 192 (pci_speed == 66666000) ? "66" : "unknown", 193 pci_clk_sel ? "sync" : "async", 194 pci_agent ? "agent" : "host", 195 pci_arb ? "arbiter" : "external-arbiter", 196 pci_info.regs); 197 198 first_free_busno = fsl_pci_init_port(&pci_info, 199 &pci1_hose, first_free_busno); 200 } else { 201 printf("PCI: disabled\n"); 202 } 203 204 puts("\n"); 205 #else 206 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 207 #endif 208 } 209 #endif 210 211 int board_early_init_r(void) 212 { 213 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 214 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 215 216 /* 217 * Remap Boot flash + PROMJET region to caching-inhibited 218 * so that flash can be erased properly. 219 */ 220 221 /* Flush d-cache and invalidate i-cache of any FLASH data */ 222 flush_dcache(); 223 invalidate_icache(); 224 225 /* invalidate existing TLB entry for flash + promjet */ 226 disable_tlb(flash_esel); 227 228 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 229 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 230 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 231 232 return 0; 233 } 234 235 int board_eth_init(bd_t *bis) 236 { 237 #ifdef CONFIG_TSEC_ENET 238 struct fsl_pq_mdio_info mdio_info; 239 struct tsec_info_struct tsec_info[2]; 240 int num = 0; 241 242 #ifdef CONFIG_TSEC1 243 SET_STD_TSEC_INFO(tsec_info[num], 1); 244 if (is_serdes_configured(SGMII_TSEC1)) { 245 puts("eTSEC1 is in sgmii mode.\n"); 246 tsec_info[num].phyaddr = 0; 247 tsec_info[num].flags |= TSEC_SGMII; 248 } 249 num++; 250 #endif 251 #ifdef CONFIG_TSEC3 252 SET_STD_TSEC_INFO(tsec_info[num], 3); 253 if (is_serdes_configured(SGMII_TSEC3)) { 254 puts("eTSEC3 is in sgmii mode.\n"); 255 tsec_info[num].phyaddr = 1; 256 tsec_info[num].flags |= TSEC_SGMII; 257 } 258 num++; 259 #endif 260 261 if (!num) { 262 printf("No TSECs initialized\n"); 263 return 0; 264 } 265 266 #ifdef CONFIG_FSL_SGMII_RISER 267 if (is_serdes_configured(SGMII_TSEC1) || 268 is_serdes_configured(SGMII_TSEC3)) { 269 fsl_sgmii_riser_init(tsec_info, num); 270 } 271 #endif 272 273 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 274 mdio_info.name = DEFAULT_MII_NAME; 275 fsl_pq_mdio_init(bis, &mdio_info); 276 277 tsec_eth_init(bis, tsec_info, num); 278 #endif 279 return pci_eth_init(bis); 280 } 281 282 #if defined(CONFIG_OF_BOARD_SETUP) 283 void ft_board_setup(void *blob, bd_t *bd) 284 { 285 ft_cpu_setup(blob, bd); 286 287 FT_FSL_PCI_SETUP; 288 289 #ifdef CONFIG_FSL_SGMII_RISER 290 fsl_sgmii_riser_fdt_fixup(blob); 291 #endif 292 } 293 #endif 294