19490a7f1SKumar Gala /* 23d7506faSramneek mehresh * Copyright 2008-2012 Freescale Semiconductor, Inc. 39490a7f1SKumar Gala * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 59490a7f1SKumar Gala */ 69490a7f1SKumar Gala 79490a7f1SKumar Gala #include <common.h> 89490a7f1SKumar Gala #include <command.h> 99490a7f1SKumar Gala #include <pci.h> 109490a7f1SKumar Gala #include <asm/processor.h> 119490a7f1SKumar Gala #include <asm/mmu.h> 127c0d4a75SKumar Gala #include <asm/cache.h> 139490a7f1SKumar Gala #include <asm/immap_85xx.h> 14c8514622SKumar Gala #include <asm/fsl_pci.h> 155614e71bSYork Sun #include <fsl_ddr_sdram.h> 169490a7f1SKumar Gala #include <asm/io.h> 1754648985SKumar Gala #include <asm/fsl_serdes.h> 189490a7f1SKumar Gala #include <spd.h> 199490a7f1SKumar Gala #include <miiphy.h> 209490a7f1SKumar Gala #include <libfdt.h> 219490a7f1SKumar Gala #include <spd_sdram.h> 229490a7f1SKumar Gala #include <fdt_support.h> 23063c1263SAndy Fleming #include <fsl_mdio.h> 242e26d837SJason Jin #include <tsec.h> 252e26d837SJason Jin #include <netdev.h> 2654a7cc49SWolfgang Denk #include <sata.h> 279490a7f1SKumar Gala 282e26d837SJason Jin #include "../common/sgmii_riser.h" 299490a7f1SKumar Gala 3080522dc8SAndy Fleming int board_early_init_f (void) 3180522dc8SAndy Fleming { 3280522dc8SAndy Fleming #ifdef CONFIG_MMC 3380522dc8SAndy Fleming volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 3480522dc8SAndy Fleming 3580522dc8SAndy Fleming setbits_be32(&gur->pmuxcr, 36ae2044d8SXie Xiaobo (MPC85xx_PMUXCR_SDHC_CD | 3780522dc8SAndy Fleming MPC85xx_PMUXCR_SDHC_WP)); 388af3d22dSXie Xiaobo 398af3d22dSXie Xiaobo /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118, 408af3d22dSXie Xiaobo * however, this erratum only applies to MPC8536 Rev1.0. 418af3d22dSXie Xiaobo * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/ 428af3d22dSXie Xiaobo if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) && 438af3d22dSXie Xiaobo (SVR_MIN(get_svr()) >= 0x1)) 448af3d22dSXie Xiaobo || (SVR_MAJ(get_svr() & 0x7) > 0x1)) 458af3d22dSXie Xiaobo setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV); 4680522dc8SAndy Fleming #endif 4780522dc8SAndy Fleming return 0; 4880522dc8SAndy Fleming } 4980522dc8SAndy Fleming 509490a7f1SKumar Gala int checkboard (void) 519490a7f1SKumar Gala { 526bb5b412SKumar Gala u8 vboot; 536bb5b412SKumar Gala u8 *pixis_base = (u8 *)PIXIS_BASE; 546bb5b412SKumar Gala 555d065c3eSTimur Tabi printf("Board: MPC8536DS Sys ID: 0x%02x, " 566bb5b412SKumar Gala "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 576bb5b412SKumar Gala in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 586bb5b412SKumar Gala in_8(pixis_base + PIXIS_PVER)); 596bb5b412SKumar Gala 606bb5b412SKumar Gala vboot = in_8(pixis_base + PIXIS_VBOOT); 616bb5b412SKumar Gala switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 626bb5b412SKumar Gala case PIXIS_VBOOT_LBMAP_NOR0: 636bb5b412SKumar Gala puts ("vBank: 0\n"); 646bb5b412SKumar Gala break; 656bb5b412SKumar Gala case PIXIS_VBOOT_LBMAP_NOR1: 666bb5b412SKumar Gala puts ("vBank: 1\n"); 676bb5b412SKumar Gala break; 686bb5b412SKumar Gala case PIXIS_VBOOT_LBMAP_NOR2: 696bb5b412SKumar Gala puts ("vBank: 2\n"); 706bb5b412SKumar Gala break; 716bb5b412SKumar Gala case PIXIS_VBOOT_LBMAP_NOR3: 726bb5b412SKumar Gala puts ("vBank: 3\n"); 736bb5b412SKumar Gala break; 746bb5b412SKumar Gala case PIXIS_VBOOT_LBMAP_PJET: 756bb5b412SKumar Gala puts ("Promjet\n"); 766bb5b412SKumar Gala break; 776bb5b412SKumar Gala case PIXIS_VBOOT_LBMAP_NAND: 786bb5b412SKumar Gala puts ("NAND\n"); 796bb5b412SKumar Gala break; 806bb5b412SKumar Gala } 816bb5b412SKumar Gala 829490a7f1SKumar Gala return 0; 839490a7f1SKumar Gala } 849490a7f1SKumar Gala 859490a7f1SKumar Gala #if !defined(CONFIG_SPD_EEPROM) 869490a7f1SKumar Gala /* 879490a7f1SKumar Gala * Fixed sdram init -- doesn't use serial presence detect. 889490a7f1SKumar Gala */ 899490a7f1SKumar Gala 909490a7f1SKumar Gala phys_size_t fixed_sdram (void) 919490a7f1SKumar Gala { 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 939a17eb5bSYork Sun struct ccsr_ddr __iomem *ddr = &immap->im_ddr; 949490a7f1SKumar Gala uint d_init; 959490a7f1SKumar Gala 966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 989490a7f1SKumar Gala 996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 1046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 1099490a7f1SKumar Gala 1109490a7f1SKumar Gala #if defined (CONFIG_DDR_ECC) 1116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 1136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->err_sbe = CONFIG_SYS_DDR_SBE; 1149490a7f1SKumar Gala #endif 1159490a7f1SKumar Gala asm("sync;isync"); 1169490a7f1SKumar Gala 1179490a7f1SKumar Gala udelay(500); 1189490a7f1SKumar Gala 1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 1209490a7f1SKumar Gala 1219490a7f1SKumar Gala #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 1229490a7f1SKumar Gala d_init = 1; 1239490a7f1SKumar Gala debug("DDR - 1st controller: memory initializing\n"); 1249490a7f1SKumar Gala /* 1259490a7f1SKumar Gala * Poll until memory is initialized. 1269490a7f1SKumar Gala * 512 Meg at 400 might hit this 200 times or so. 1279490a7f1SKumar Gala */ 1289490a7f1SKumar Gala while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 1299490a7f1SKumar Gala udelay(1000); 1309490a7f1SKumar Gala } 1319490a7f1SKumar Gala debug("DDR: memory initialized\n\n"); 1329490a7f1SKumar Gala asm("sync; isync"); 1339490a7f1SKumar Gala udelay(500); 1349490a7f1SKumar Gala #endif 1359490a7f1SKumar Gala 1369490a7f1SKumar Gala return 512 * 1024 * 1024; 1379490a7f1SKumar Gala } 1389490a7f1SKumar Gala 1399490a7f1SKumar Gala #endif 1409490a7f1SKumar Gala 1419490a7f1SKumar Gala #ifdef CONFIG_PCI1 1429490a7f1SKumar Gala static struct pci_controller pci1_hose; 1439490a7f1SKumar Gala #endif 1449490a7f1SKumar Gala 1458a414c42SMingkai Hu #ifdef CONFIG_PCI 1468a414c42SMingkai Hu void pci_init_board(void) 1479490a7f1SKumar Gala { 1488a414c42SMingkai Hu ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 1495f7b31b0SKumar Gala struct fsl_pci_info pci_info; 1505f7b31b0SKumar Gala u32 devdisr, pordevsr; 1518a414c42SMingkai Hu u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 1525f7b31b0SKumar Gala int first_free_busno; 1539490a7f1SKumar Gala 1545f7b31b0SKumar Gala first_free_busno = fsl_pcie_init_board(0); 1558a414c42SMingkai Hu 1565f7b31b0SKumar Gala #ifdef CONFIG_PCI1 1578a414c42SMingkai Hu devdisr = in_be32(&gur->devdisr); 1588a414c42SMingkai Hu pordevsr = in_be32(&gur->pordevsr); 1598a414c42SMingkai Hu porpllsr = in_be32(&gur->porpllsr); 1608a414c42SMingkai Hu 1618a414c42SMingkai Hu pci_speed = 66666000; 1628a414c42SMingkai Hu pci_32 = 1; 1638a414c42SMingkai Hu pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 1648a414c42SMingkai Hu pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 1659490a7f1SKumar Gala 1669490a7f1SKumar Gala if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 1675f7b31b0SKumar Gala SET_STD_PCI_INFO(pci_info, 1); 1685f7b31b0SKumar Gala set_next_law(pci_info.mem_phys, 1695f7b31b0SKumar Gala law_size_bits(pci_info.mem_size), pci_info.law); 1705f7b31b0SKumar Gala set_next_law(pci_info.io_phys, 1715f7b31b0SKumar Gala law_size_bits(pci_info.io_size), pci_info.law); 1725f7b31b0SKumar Gala 1735f7b31b0SKumar Gala pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 1748ca78f2cSPeter Tyser printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 1759490a7f1SKumar Gala (pci_32) ? 32 : 64, 1769490a7f1SKumar Gala (pci_speed == 33333000) ? "33" : 1779490a7f1SKumar Gala (pci_speed == 66666000) ? "66" : "unknown", 1789490a7f1SKumar Gala pci_clk_sel ? "sync" : "async", 1799490a7f1SKumar Gala pci_agent ? "agent" : "host", 1809490a7f1SKumar Gala pci_arb ? "arbiter" : "external-arbiter", 1815f7b31b0SKumar Gala pci_info.regs); 1829490a7f1SKumar Gala 1835f7b31b0SKumar Gala first_free_busno = fsl_pci_init_port(&pci_info, 1848a414c42SMingkai Hu &pci1_hose, first_free_busno); 1859490a7f1SKumar Gala } else { 1869490a7f1SKumar Gala printf("PCI: disabled\n"); 1879490a7f1SKumar Gala } 1888a414c42SMingkai Hu 1898a414c42SMingkai Hu puts("\n"); 1909490a7f1SKumar Gala #else 1918a414c42SMingkai Hu setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 1929490a7f1SKumar Gala #endif 1939490a7f1SKumar Gala } 1948a414c42SMingkai Hu #endif 1959490a7f1SKumar Gala 1969490a7f1SKumar Gala int board_early_init_r(void) 1979490a7f1SKumar Gala { 1986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 1999d045682SYork Sun int flash_esel = find_tlb_idx((void *)flashbase, 1); 2009490a7f1SKumar Gala 2019490a7f1SKumar Gala /* 2029490a7f1SKumar Gala * Remap Boot flash + PROMJET region to caching-inhibited 2039490a7f1SKumar Gala * so that flash can be erased properly. 2049490a7f1SKumar Gala */ 2059490a7f1SKumar Gala 2067c0d4a75SKumar Gala /* Flush d-cache and invalidate i-cache of any FLASH data */ 2077c0d4a75SKumar Gala flush_dcache(); 2087c0d4a75SKumar Gala invalidate_icache(); 2099490a7f1SKumar Gala 2109d045682SYork Sun if (flash_esel == -1) { 2119d045682SYork Sun /* very unlikely unless something is messed up */ 2129d045682SYork Sun puts("Error: Could not find TLB for FLASH BASE\n"); 2139d045682SYork Sun flash_esel = 1; /* give our best effort to continue */ 2149d045682SYork Sun } else { 2159490a7f1SKumar Gala /* invalidate existing TLB entry for flash + promjet */ 2169490a7f1SKumar Gala disable_tlb(flash_esel); 2179d045682SYork Sun } 2189490a7f1SKumar Gala 219c953ddfdSKumar Gala set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 2209490a7f1SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 2219490a7f1SKumar Gala 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 2229490a7f1SKumar Gala 2239490a7f1SKumar Gala return 0; 2249490a7f1SKumar Gala } 2259490a7f1SKumar Gala 2262e26d837SJason Jin int board_eth_init(bd_t *bis) 2272e26d837SJason Jin { 2282e26d837SJason Jin #ifdef CONFIG_TSEC_ENET 229063c1263SAndy Fleming struct fsl_pq_mdio_info mdio_info; 2302e26d837SJason Jin struct tsec_info_struct tsec_info[2]; 2312e26d837SJason Jin int num = 0; 2322e26d837SJason Jin 2332e26d837SJason Jin #ifdef CONFIG_TSEC1 2342e26d837SJason Jin SET_STD_TSEC_INFO(tsec_info[num], 1); 235058d7dc7SKumar Gala if (is_serdes_configured(SGMII_TSEC1)) { 236058d7dc7SKumar Gala puts("eTSEC1 is in sgmii mode.\n"); 2372e26d837SJason Jin tsec_info[num].phyaddr = 0; 2382e26d837SJason Jin tsec_info[num].flags |= TSEC_SGMII; 2392e26d837SJason Jin } 2402e26d837SJason Jin num++; 2412e26d837SJason Jin #endif 2422e26d837SJason Jin #ifdef CONFIG_TSEC3 2432e26d837SJason Jin SET_STD_TSEC_INFO(tsec_info[num], 3); 244058d7dc7SKumar Gala if (is_serdes_configured(SGMII_TSEC3)) { 245058d7dc7SKumar Gala puts("eTSEC3 is in sgmii mode.\n"); 2462e26d837SJason Jin tsec_info[num].phyaddr = 1; 2472e26d837SJason Jin tsec_info[num].flags |= TSEC_SGMII; 2482e26d837SJason Jin } 2492e26d837SJason Jin num++; 2502e26d837SJason Jin #endif 2512e26d837SJason Jin 2522e26d837SJason Jin if (!num) { 2532e26d837SJason Jin printf("No TSECs initialized\n"); 2542e26d837SJason Jin return 0; 2552e26d837SJason Jin } 2562e26d837SJason Jin 257feede8b0SAndy Fleming #ifdef CONFIG_FSL_SGMII_RISER 258058d7dc7SKumar Gala if (is_serdes_configured(SGMII_TSEC1) || 259058d7dc7SKumar Gala is_serdes_configured(SGMII_TSEC3)) { 2602e26d837SJason Jin fsl_sgmii_riser_init(tsec_info, num); 261058d7dc7SKumar Gala } 262feede8b0SAndy Fleming #endif 2632e26d837SJason Jin 264063c1263SAndy Fleming mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 265063c1263SAndy Fleming mdio_info.name = DEFAULT_MII_NAME; 266063c1263SAndy Fleming fsl_pq_mdio_init(bis, &mdio_info); 267063c1263SAndy Fleming 2682e26d837SJason Jin tsec_eth_init(bis, tsec_info, num); 2692e26d837SJason Jin #endif 2702e26d837SJason Jin return pci_eth_init(bis); 2712e26d837SJason Jin } 2722e26d837SJason Jin 2739490a7f1SKumar Gala #if defined(CONFIG_OF_BOARD_SETUP) 274*e895a4b0SSimon Glass int ft_board_setup(void *blob, bd_t *bd) 2752dba0deaSKumar Gala { 2769490a7f1SKumar Gala ft_cpu_setup(blob, bd); 2779490a7f1SKumar Gala 2786525d51fSKumar Gala FT_FSL_PCI_SETUP; 2796525d51fSKumar Gala 280feede8b0SAndy Fleming #ifdef CONFIG_FSL_SGMII_RISER 281feede8b0SAndy Fleming fsl_sgmii_riser_fdt_fixup(blob); 282feede8b0SAndy Fleming #endif 2833d7506faSramneek mehresh 2843d7506faSramneek mehresh #ifdef CONFIG_HAS_FSL_MPH_USB 2853d7506faSramneek mehresh fdt_fixup_dr_usb(blob, bd); 2863d7506faSramneek mehresh #endif 2873d7506faSramneek mehresh 288*e895a4b0SSimon Glass return 0; 2899490a7f1SKumar Gala } 2909490a7f1SKumar Gala #endif 291