19490a7f1SKumar Gala /* 2*3d7506faSramneek mehresh * Copyright 2008-2012 Freescale Semiconductor, Inc. 39490a7f1SKumar Gala * 49490a7f1SKumar Gala * See file CREDITS for list of people who contributed to this 59490a7f1SKumar Gala * project. 69490a7f1SKumar Gala * 79490a7f1SKumar Gala * This program is free software; you can redistribute it and/or 89490a7f1SKumar Gala * modify it under the terms of the GNU General Public License as 99490a7f1SKumar Gala * published by the Free Software Foundation; either version 2 of 109490a7f1SKumar Gala * the License, or (at your option) any later version. 119490a7f1SKumar Gala * 129490a7f1SKumar Gala * This program is distributed in the hope that it will be useful, 139490a7f1SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 149490a7f1SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 159490a7f1SKumar Gala * GNU General Public License for more details. 169490a7f1SKumar Gala * 179490a7f1SKumar Gala * You should have received a copy of the GNU General Public License 189490a7f1SKumar Gala * along with this program; if not, write to the Free Software 199490a7f1SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 209490a7f1SKumar Gala * MA 02111-1307 USA 219490a7f1SKumar Gala */ 229490a7f1SKumar Gala 239490a7f1SKumar Gala #include <common.h> 249490a7f1SKumar Gala #include <command.h> 259490a7f1SKumar Gala #include <pci.h> 269490a7f1SKumar Gala #include <asm/processor.h> 279490a7f1SKumar Gala #include <asm/mmu.h> 287c0d4a75SKumar Gala #include <asm/cache.h> 299490a7f1SKumar Gala #include <asm/immap_85xx.h> 30c8514622SKumar Gala #include <asm/fsl_pci.h> 319490a7f1SKumar Gala #include <asm/fsl_ddr_sdram.h> 329490a7f1SKumar Gala #include <asm/io.h> 3354648985SKumar Gala #include <asm/fsl_serdes.h> 349490a7f1SKumar Gala #include <spd.h> 359490a7f1SKumar Gala #include <miiphy.h> 369490a7f1SKumar Gala #include <libfdt.h> 379490a7f1SKumar Gala #include <spd_sdram.h> 389490a7f1SKumar Gala #include <fdt_support.h> 39063c1263SAndy Fleming #include <fsl_mdio.h> 402e26d837SJason Jin #include <tsec.h> 412e26d837SJason Jin #include <netdev.h> 4254a7cc49SWolfgang Denk #include <sata.h> 439490a7f1SKumar Gala 442e26d837SJason Jin #include "../common/sgmii_riser.h" 459490a7f1SKumar Gala 4680522dc8SAndy Fleming int board_early_init_f (void) 4780522dc8SAndy Fleming { 4880522dc8SAndy Fleming #ifdef CONFIG_MMC 4980522dc8SAndy Fleming volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 5080522dc8SAndy Fleming 5180522dc8SAndy Fleming setbits_be32(&gur->pmuxcr, 52ae2044d8SXie Xiaobo (MPC85xx_PMUXCR_SDHC_CD | 5380522dc8SAndy Fleming MPC85xx_PMUXCR_SDHC_WP)); 548af3d22dSXie Xiaobo 558af3d22dSXie Xiaobo /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118, 568af3d22dSXie Xiaobo * however, this erratum only applies to MPC8536 Rev1.0. 578af3d22dSXie Xiaobo * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/ 588af3d22dSXie Xiaobo if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) && 598af3d22dSXie Xiaobo (SVR_MIN(get_svr()) >= 0x1)) 608af3d22dSXie Xiaobo || (SVR_MAJ(get_svr() & 0x7) > 0x1)) 618af3d22dSXie Xiaobo setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV); 6280522dc8SAndy Fleming #endif 6380522dc8SAndy Fleming return 0; 6480522dc8SAndy Fleming } 6580522dc8SAndy Fleming 669490a7f1SKumar Gala int checkboard (void) 679490a7f1SKumar Gala { 686bb5b412SKumar Gala u8 vboot; 696bb5b412SKumar Gala u8 *pixis_base = (u8 *)PIXIS_BASE; 706bb5b412SKumar Gala 715d065c3eSTimur Tabi printf("Board: MPC8536DS Sys ID: 0x%02x, " 726bb5b412SKumar Gala "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 736bb5b412SKumar Gala in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 746bb5b412SKumar Gala in_8(pixis_base + PIXIS_PVER)); 756bb5b412SKumar Gala 766bb5b412SKumar Gala vboot = in_8(pixis_base + PIXIS_VBOOT); 776bb5b412SKumar Gala switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 786bb5b412SKumar Gala case PIXIS_VBOOT_LBMAP_NOR0: 796bb5b412SKumar Gala puts ("vBank: 0\n"); 806bb5b412SKumar Gala break; 816bb5b412SKumar Gala case PIXIS_VBOOT_LBMAP_NOR1: 826bb5b412SKumar Gala puts ("vBank: 1\n"); 836bb5b412SKumar Gala break; 846bb5b412SKumar Gala case PIXIS_VBOOT_LBMAP_NOR2: 856bb5b412SKumar Gala puts ("vBank: 2\n"); 866bb5b412SKumar Gala break; 876bb5b412SKumar Gala case PIXIS_VBOOT_LBMAP_NOR3: 886bb5b412SKumar Gala puts ("vBank: 3\n"); 896bb5b412SKumar Gala break; 906bb5b412SKumar Gala case PIXIS_VBOOT_LBMAP_PJET: 916bb5b412SKumar Gala puts ("Promjet\n"); 926bb5b412SKumar Gala break; 936bb5b412SKumar Gala case PIXIS_VBOOT_LBMAP_NAND: 946bb5b412SKumar Gala puts ("NAND\n"); 956bb5b412SKumar Gala break; 966bb5b412SKumar Gala } 976bb5b412SKumar Gala 989490a7f1SKumar Gala return 0; 999490a7f1SKumar Gala } 1009490a7f1SKumar Gala 1019490a7f1SKumar Gala #if !defined(CONFIG_SPD_EEPROM) 1029490a7f1SKumar Gala /* 1039490a7f1SKumar Gala * Fixed sdram init -- doesn't use serial presence detect. 1049490a7f1SKumar Gala */ 1059490a7f1SKumar Gala 1069490a7f1SKumar Gala phys_size_t fixed_sdram (void) 1079490a7f1SKumar Gala { 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 1099490a7f1SKumar Gala volatile ccsr_ddr_t *ddr= &immap->im_ddr; 1109490a7f1SKumar Gala uint d_init; 1119490a7f1SKumar Gala 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 1136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 1149490a7f1SKumar Gala 1156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 1166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 1176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 1216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 1226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 1236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 1259490a7f1SKumar Gala 1269490a7f1SKumar Gala #if defined (CONFIG_DDR_ECC) 1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 1286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 1296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->err_sbe = CONFIG_SYS_DDR_SBE; 1309490a7f1SKumar Gala #endif 1319490a7f1SKumar Gala asm("sync;isync"); 1329490a7f1SKumar Gala 1339490a7f1SKumar Gala udelay(500); 1349490a7f1SKumar Gala 1356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 1369490a7f1SKumar Gala 1379490a7f1SKumar Gala #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 1389490a7f1SKumar Gala d_init = 1; 1399490a7f1SKumar Gala debug("DDR - 1st controller: memory initializing\n"); 1409490a7f1SKumar Gala /* 1419490a7f1SKumar Gala * Poll until memory is initialized. 1429490a7f1SKumar Gala * 512 Meg at 400 might hit this 200 times or so. 1439490a7f1SKumar Gala */ 1449490a7f1SKumar Gala while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 1459490a7f1SKumar Gala udelay(1000); 1469490a7f1SKumar Gala } 1479490a7f1SKumar Gala debug("DDR: memory initialized\n\n"); 1489490a7f1SKumar Gala asm("sync; isync"); 1499490a7f1SKumar Gala udelay(500); 1509490a7f1SKumar Gala #endif 1519490a7f1SKumar Gala 1529490a7f1SKumar Gala return 512 * 1024 * 1024; 1539490a7f1SKumar Gala } 1549490a7f1SKumar Gala 1559490a7f1SKumar Gala #endif 1569490a7f1SKumar Gala 1579490a7f1SKumar Gala #ifdef CONFIG_PCI1 1589490a7f1SKumar Gala static struct pci_controller pci1_hose; 1599490a7f1SKumar Gala #endif 1609490a7f1SKumar Gala 1618a414c42SMingkai Hu #ifdef CONFIG_PCI 1628a414c42SMingkai Hu void pci_init_board(void) 1639490a7f1SKumar Gala { 1648a414c42SMingkai Hu ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 1655f7b31b0SKumar Gala struct fsl_pci_info pci_info; 1665f7b31b0SKumar Gala u32 devdisr, pordevsr; 1678a414c42SMingkai Hu u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 1685f7b31b0SKumar Gala int first_free_busno; 1699490a7f1SKumar Gala 1705f7b31b0SKumar Gala first_free_busno = fsl_pcie_init_board(0); 1718a414c42SMingkai Hu 1725f7b31b0SKumar Gala #ifdef CONFIG_PCI1 1738a414c42SMingkai Hu devdisr = in_be32(&gur->devdisr); 1748a414c42SMingkai Hu pordevsr = in_be32(&gur->pordevsr); 1758a414c42SMingkai Hu porpllsr = in_be32(&gur->porpllsr); 1768a414c42SMingkai Hu 1778a414c42SMingkai Hu pci_speed = 66666000; 1788a414c42SMingkai Hu pci_32 = 1; 1798a414c42SMingkai Hu pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 1808a414c42SMingkai Hu pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 1819490a7f1SKumar Gala 1829490a7f1SKumar Gala if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 1835f7b31b0SKumar Gala SET_STD_PCI_INFO(pci_info, 1); 1845f7b31b0SKumar Gala set_next_law(pci_info.mem_phys, 1855f7b31b0SKumar Gala law_size_bits(pci_info.mem_size), pci_info.law); 1865f7b31b0SKumar Gala set_next_law(pci_info.io_phys, 1875f7b31b0SKumar Gala law_size_bits(pci_info.io_size), pci_info.law); 1885f7b31b0SKumar Gala 1895f7b31b0SKumar Gala pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 1908ca78f2cSPeter Tyser printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 1919490a7f1SKumar Gala (pci_32) ? 32 : 64, 1929490a7f1SKumar Gala (pci_speed == 33333000) ? "33" : 1939490a7f1SKumar Gala (pci_speed == 66666000) ? "66" : "unknown", 1949490a7f1SKumar Gala pci_clk_sel ? "sync" : "async", 1959490a7f1SKumar Gala pci_agent ? "agent" : "host", 1969490a7f1SKumar Gala pci_arb ? "arbiter" : "external-arbiter", 1975f7b31b0SKumar Gala pci_info.regs); 1989490a7f1SKumar Gala 1995f7b31b0SKumar Gala first_free_busno = fsl_pci_init_port(&pci_info, 2008a414c42SMingkai Hu &pci1_hose, first_free_busno); 2019490a7f1SKumar Gala } else { 2029490a7f1SKumar Gala printf("PCI: disabled\n"); 2039490a7f1SKumar Gala } 2048a414c42SMingkai Hu 2058a414c42SMingkai Hu puts("\n"); 2069490a7f1SKumar Gala #else 2078a414c42SMingkai Hu setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 2089490a7f1SKumar Gala #endif 2099490a7f1SKumar Gala } 2108a414c42SMingkai Hu #endif 2119490a7f1SKumar Gala 2129490a7f1SKumar Gala int board_early_init_r(void) 2139490a7f1SKumar Gala { 2146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 2155fb6ea3aSKumar Gala const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 2169490a7f1SKumar Gala 2179490a7f1SKumar Gala /* 2189490a7f1SKumar Gala * Remap Boot flash + PROMJET region to caching-inhibited 2199490a7f1SKumar Gala * so that flash can be erased properly. 2209490a7f1SKumar Gala */ 2219490a7f1SKumar Gala 2227c0d4a75SKumar Gala /* Flush d-cache and invalidate i-cache of any FLASH data */ 2237c0d4a75SKumar Gala flush_dcache(); 2247c0d4a75SKumar Gala invalidate_icache(); 2259490a7f1SKumar Gala 2269490a7f1SKumar Gala /* invalidate existing TLB entry for flash + promjet */ 2279490a7f1SKumar Gala disable_tlb(flash_esel); 2289490a7f1SKumar Gala 229c953ddfdSKumar Gala set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 2309490a7f1SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 2319490a7f1SKumar Gala 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 2329490a7f1SKumar Gala 2339490a7f1SKumar Gala return 0; 2349490a7f1SKumar Gala } 2359490a7f1SKumar Gala 2362e26d837SJason Jin int board_eth_init(bd_t *bis) 2372e26d837SJason Jin { 2382e26d837SJason Jin #ifdef CONFIG_TSEC_ENET 239063c1263SAndy Fleming struct fsl_pq_mdio_info mdio_info; 2402e26d837SJason Jin struct tsec_info_struct tsec_info[2]; 2412e26d837SJason Jin int num = 0; 2422e26d837SJason Jin 2432e26d837SJason Jin #ifdef CONFIG_TSEC1 2442e26d837SJason Jin SET_STD_TSEC_INFO(tsec_info[num], 1); 245058d7dc7SKumar Gala if (is_serdes_configured(SGMII_TSEC1)) { 246058d7dc7SKumar Gala puts("eTSEC1 is in sgmii mode.\n"); 2472e26d837SJason Jin tsec_info[num].phyaddr = 0; 2482e26d837SJason Jin tsec_info[num].flags |= TSEC_SGMII; 2492e26d837SJason Jin } 2502e26d837SJason Jin num++; 2512e26d837SJason Jin #endif 2522e26d837SJason Jin #ifdef CONFIG_TSEC3 2532e26d837SJason Jin SET_STD_TSEC_INFO(tsec_info[num], 3); 254058d7dc7SKumar Gala if (is_serdes_configured(SGMII_TSEC3)) { 255058d7dc7SKumar Gala puts("eTSEC3 is in sgmii mode.\n"); 2562e26d837SJason Jin tsec_info[num].phyaddr = 1; 2572e26d837SJason Jin tsec_info[num].flags |= TSEC_SGMII; 2582e26d837SJason Jin } 2592e26d837SJason Jin num++; 2602e26d837SJason Jin #endif 2612e26d837SJason Jin 2622e26d837SJason Jin if (!num) { 2632e26d837SJason Jin printf("No TSECs initialized\n"); 2642e26d837SJason Jin return 0; 2652e26d837SJason Jin } 2662e26d837SJason Jin 267feede8b0SAndy Fleming #ifdef CONFIG_FSL_SGMII_RISER 268058d7dc7SKumar Gala if (is_serdes_configured(SGMII_TSEC1) || 269058d7dc7SKumar Gala is_serdes_configured(SGMII_TSEC3)) { 2702e26d837SJason Jin fsl_sgmii_riser_init(tsec_info, num); 271058d7dc7SKumar Gala } 272feede8b0SAndy Fleming #endif 2732e26d837SJason Jin 274063c1263SAndy Fleming mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 275063c1263SAndy Fleming mdio_info.name = DEFAULT_MII_NAME; 276063c1263SAndy Fleming fsl_pq_mdio_init(bis, &mdio_info); 277063c1263SAndy Fleming 2782e26d837SJason Jin tsec_eth_init(bis, tsec_info, num); 2792e26d837SJason Jin #endif 2802e26d837SJason Jin return pci_eth_init(bis); 2812e26d837SJason Jin } 2822e26d837SJason Jin 2839490a7f1SKumar Gala #if defined(CONFIG_OF_BOARD_SETUP) 2842dba0deaSKumar Gala void ft_board_setup(void *blob, bd_t *bd) 2852dba0deaSKumar Gala { 2869490a7f1SKumar Gala ft_cpu_setup(blob, bd); 2879490a7f1SKumar Gala 2886525d51fSKumar Gala FT_FSL_PCI_SETUP; 2896525d51fSKumar Gala 290feede8b0SAndy Fleming #ifdef CONFIG_FSL_SGMII_RISER 291feede8b0SAndy Fleming fsl_sgmii_riser_fdt_fixup(blob); 292feede8b0SAndy Fleming #endif 293*3d7506faSramneek mehresh 294*3d7506faSramneek mehresh #ifdef CONFIG_HAS_FSL_MPH_USB 295*3d7506faSramneek mehresh fdt_fixup_dr_usb(blob, bd); 296*3d7506faSramneek mehresh #endif 297*3d7506faSramneek mehresh 2989490a7f1SKumar Gala } 2999490a7f1SKumar Gala #endif 300