19490a7f1SKumar Gala /* 29490a7f1SKumar Gala * Copyright 2008 Freescale Semiconductor. 39490a7f1SKumar Gala * 49490a7f1SKumar Gala * See file CREDITS for list of people who contributed to this 59490a7f1SKumar Gala * project. 69490a7f1SKumar Gala * 79490a7f1SKumar Gala * This program is free software; you can redistribute it and/or 89490a7f1SKumar Gala * modify it under the terms of the GNU General Public License as 99490a7f1SKumar Gala * published by the Free Software Foundation; either version 2 of 109490a7f1SKumar Gala * the License, or (at your option) any later version. 119490a7f1SKumar Gala * 129490a7f1SKumar Gala * This program is distributed in the hope that it will be useful, 139490a7f1SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 149490a7f1SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 159490a7f1SKumar Gala * GNU General Public License for more details. 169490a7f1SKumar Gala * 179490a7f1SKumar Gala * You should have received a copy of the GNU General Public License 189490a7f1SKumar Gala * along with this program; if not, write to the Free Software 199490a7f1SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 209490a7f1SKumar Gala * MA 02111-1307 USA 219490a7f1SKumar Gala */ 229490a7f1SKumar Gala 239490a7f1SKumar Gala #include <common.h> 249490a7f1SKumar Gala #include <command.h> 259490a7f1SKumar Gala #include <pci.h> 269490a7f1SKumar Gala #include <asm/processor.h> 279490a7f1SKumar Gala #include <asm/mmu.h> 287c0d4a75SKumar Gala #include <asm/cache.h> 299490a7f1SKumar Gala #include <asm/immap_85xx.h> 309490a7f1SKumar Gala #include <asm/immap_fsl_pci.h> 319490a7f1SKumar Gala #include <asm/fsl_ddr_sdram.h> 329490a7f1SKumar Gala #include <asm/io.h> 339490a7f1SKumar Gala #include <spd.h> 349490a7f1SKumar Gala #include <miiphy.h> 359490a7f1SKumar Gala #include <libfdt.h> 369490a7f1SKumar Gala #include <spd_sdram.h> 379490a7f1SKumar Gala #include <fdt_support.h> 38*2e26d837SJason Jin #include <tsec.h> 39*2e26d837SJason Jin #include <netdev.h> 409490a7f1SKumar Gala 419490a7f1SKumar Gala #include "../common/pixis.h" 42*2e26d837SJason Jin #include "../common/sgmii_riser.h" 439490a7f1SKumar Gala 449490a7f1SKumar Gala #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 459490a7f1SKumar Gala extern void ddr_enable_ecc(unsigned int dram_size); 469490a7f1SKumar Gala #endif 479490a7f1SKumar Gala 489490a7f1SKumar Gala phys_size_t fixed_sdram(void); 499490a7f1SKumar Gala 509490a7f1SKumar Gala int checkboard (void) 519490a7f1SKumar Gala { 529490a7f1SKumar Gala printf ("Board: MPC8536DS, System ID: 0x%02x, " 539490a7f1SKumar Gala "System Version: 0x%02x, FPGA Version: 0x%02x\n", 549490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 559490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_PVER)); 569490a7f1SKumar Gala return 0; 579490a7f1SKumar Gala } 589490a7f1SKumar Gala 599490a7f1SKumar Gala phys_size_t 609490a7f1SKumar Gala initdram(int board_type) 619490a7f1SKumar Gala { 629490a7f1SKumar Gala phys_size_t dram_size = 0; 639490a7f1SKumar Gala 649490a7f1SKumar Gala puts("Initializing...."); 659490a7f1SKumar Gala 669490a7f1SKumar Gala #ifdef CONFIG_SPD_EEPROM 679490a7f1SKumar Gala dram_size = fsl_ddr_sdram(); 689490a7f1SKumar Gala 699490a7f1SKumar Gala dram_size = setup_ddr_tlbs(dram_size / 0x100000); 709490a7f1SKumar Gala 719490a7f1SKumar Gala dram_size *= 0x100000; 729490a7f1SKumar Gala #else 739490a7f1SKumar Gala dram_size = fixed_sdram(); 749490a7f1SKumar Gala #endif 759490a7f1SKumar Gala 769490a7f1SKumar Gala #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 779490a7f1SKumar Gala /* 789490a7f1SKumar Gala * Initialize and enable DDR ECC. 799490a7f1SKumar Gala */ 809490a7f1SKumar Gala ddr_enable_ecc(dram_size); 819490a7f1SKumar Gala #endif 829490a7f1SKumar Gala puts(" DDR: "); 839490a7f1SKumar Gala return dram_size; 849490a7f1SKumar Gala } 859490a7f1SKumar Gala 869490a7f1SKumar Gala #if !defined(CONFIG_SPD_EEPROM) 879490a7f1SKumar Gala /* 889490a7f1SKumar Gala * Fixed sdram init -- doesn't use serial presence detect. 899490a7f1SKumar Gala */ 909490a7f1SKumar Gala 919490a7f1SKumar Gala phys_size_t fixed_sdram (void) 929490a7f1SKumar Gala { 936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 949490a7f1SKumar Gala volatile ccsr_ddr_t *ddr= &immap->im_ddr; 959490a7f1SKumar Gala uint d_init; 969490a7f1SKumar Gala 976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 999490a7f1SKumar Gala 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 1046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 1096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 1109490a7f1SKumar Gala 1119490a7f1SKumar Gala #if defined (CONFIG_DDR_ECC) 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 1136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->err_sbe = CONFIG_SYS_DDR_SBE; 1159490a7f1SKumar Gala #endif 1169490a7f1SKumar Gala asm("sync;isync"); 1179490a7f1SKumar Gala 1189490a7f1SKumar Gala udelay(500); 1199490a7f1SKumar Gala 1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 1219490a7f1SKumar Gala 1229490a7f1SKumar Gala #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 1239490a7f1SKumar Gala d_init = 1; 1249490a7f1SKumar Gala debug("DDR - 1st controller: memory initializing\n"); 1259490a7f1SKumar Gala /* 1269490a7f1SKumar Gala * Poll until memory is initialized. 1279490a7f1SKumar Gala * 512 Meg at 400 might hit this 200 times or so. 1289490a7f1SKumar Gala */ 1299490a7f1SKumar Gala while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 1309490a7f1SKumar Gala udelay(1000); 1319490a7f1SKumar Gala } 1329490a7f1SKumar Gala debug("DDR: memory initialized\n\n"); 1339490a7f1SKumar Gala asm("sync; isync"); 1349490a7f1SKumar Gala udelay(500); 1359490a7f1SKumar Gala #endif 1369490a7f1SKumar Gala 1379490a7f1SKumar Gala return 512 * 1024 * 1024; 1389490a7f1SKumar Gala } 1399490a7f1SKumar Gala 1409490a7f1SKumar Gala #endif 1419490a7f1SKumar Gala 1429490a7f1SKumar Gala #ifdef CONFIG_PCI1 1439490a7f1SKumar Gala static struct pci_controller pci1_hose; 1449490a7f1SKumar Gala #endif 1459490a7f1SKumar Gala 1469490a7f1SKumar Gala #ifdef CONFIG_PCIE1 1479490a7f1SKumar Gala static struct pci_controller pcie1_hose; 1489490a7f1SKumar Gala #endif 1499490a7f1SKumar Gala 1509490a7f1SKumar Gala #ifdef CONFIG_PCIE2 1519490a7f1SKumar Gala static struct pci_controller pcie2_hose; 1529490a7f1SKumar Gala #endif 1539490a7f1SKumar Gala 1549490a7f1SKumar Gala #ifdef CONFIG_PCIE3 1559490a7f1SKumar Gala static struct pci_controller pcie3_hose; 1569490a7f1SKumar Gala #endif 1579490a7f1SKumar Gala 1589490a7f1SKumar Gala int first_free_busno=0; 1599490a7f1SKumar Gala 1609490a7f1SKumar Gala void 1619490a7f1SKumar Gala pci_init_board(void) 1629490a7f1SKumar Gala { 1636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 1649490a7f1SKumar Gala uint devdisr = gur->devdisr; 1659490a7f1SKumar Gala uint sdrs2_io_sel = 1669490a7f1SKumar Gala (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 1679490a7f1SKumar Gala uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 1689490a7f1SKumar Gala uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 1699490a7f1SKumar Gala 1709490a7f1SKumar Gala debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ 1719490a7f1SKumar Gala host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); 1729490a7f1SKumar Gala 1739490a7f1SKumar Gala if (sdrs2_io_sel == 7) 1749490a7f1SKumar Gala printf(" Serdes2 disalbed\n"); 1759490a7f1SKumar Gala else if (sdrs2_io_sel == 4) { 1769490a7f1SKumar Gala printf(" eTSEC1 is in sgmii mode.\n"); 1779490a7f1SKumar Gala printf(" eTSEC3 is in sgmii mode.\n"); 1789490a7f1SKumar Gala } else if (sdrs2_io_sel == 6) 1799490a7f1SKumar Gala printf(" eTSEC1 is in sgmii mode.\n"); 1809490a7f1SKumar Gala 1819490a7f1SKumar Gala #ifdef CONFIG_PCIE3 1829490a7f1SKumar Gala { 1836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 1849490a7f1SKumar Gala extern void fsl_pci_init(struct pci_controller *hose); 1859490a7f1SKumar Gala struct pci_controller *hose = &pcie3_hose; 1869490a7f1SKumar Gala int pcie_ep = (host_agent == 1); 1879490a7f1SKumar Gala int pcie_configured = (io_sel == 7); 1889490a7f1SKumar Gala 1899490a7f1SKumar Gala if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 1909490a7f1SKumar Gala printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", 1919490a7f1SKumar Gala pcie_ep ? "End Point" : "Root Complex", 1929490a7f1SKumar Gala (uint)pci); 1939490a7f1SKumar Gala if (pci->pme_msg_det) { 1949490a7f1SKumar Gala pci->pme_msg_det = 0xffffffff; 1959490a7f1SKumar Gala debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 1969490a7f1SKumar Gala } 1979490a7f1SKumar Gala printf ("\n"); 1989490a7f1SKumar Gala 1999490a7f1SKumar Gala /* inbound */ 2009490a7f1SKumar Gala pci_set_region(hose->regions + 0, 2016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI_MEMORY_BUS, 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI_MEMORY_PHYS, 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI_MEMORY_SIZE, 2049490a7f1SKumar Gala PCI_REGION_MEM | PCI_REGION_MEMORY); 2059490a7f1SKumar Gala 2069490a7f1SKumar Gala /* outbound memory */ 2079490a7f1SKumar Gala pci_set_region(hose->regions + 1, 2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE3_MEM_BASE, 2096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE3_MEM_PHYS, 2106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE3_MEM_SIZE, 2119490a7f1SKumar Gala PCI_REGION_MEM); 2129490a7f1SKumar Gala 2139490a7f1SKumar Gala /* outbound io */ 2149490a7f1SKumar Gala pci_set_region(hose->regions + 2, 2156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE3_IO_BASE, 2166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE3_IO_PHYS, 2176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE3_IO_SIZE, 2189490a7f1SKumar Gala PCI_REGION_IO); 2199490a7f1SKumar Gala 2209490a7f1SKumar Gala hose->region_count = 3; 2219490a7f1SKumar Gala 2229490a7f1SKumar Gala hose->first_busno=first_free_busno; 2239490a7f1SKumar Gala pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 2249490a7f1SKumar Gala 2259490a7f1SKumar Gala fsl_pci_init(hose); 2269490a7f1SKumar Gala 2279490a7f1SKumar Gala first_free_busno=hose->last_busno+1; 2289490a7f1SKumar Gala printf (" PCIE3 on bus %02x - %02x\n", 2299490a7f1SKumar Gala hose->first_busno,hose->last_busno); 2309490a7f1SKumar Gala } else { 2319490a7f1SKumar Gala printf (" PCIE3: disabled\n"); 2329490a7f1SKumar Gala } 2339490a7f1SKumar Gala 2349490a7f1SKumar Gala } 2359490a7f1SKumar Gala #else 2369490a7f1SKumar Gala gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 2379490a7f1SKumar Gala #endif 2389490a7f1SKumar Gala 2399490a7f1SKumar Gala #ifdef CONFIG_PCIE1 2409490a7f1SKumar Gala { 2416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 2429490a7f1SKumar Gala extern void fsl_pci_init(struct pci_controller *hose); 2439490a7f1SKumar Gala struct pci_controller *hose = &pcie1_hose; 2449490a7f1SKumar Gala int pcie_ep = (host_agent == 5); 2459490a7f1SKumar Gala int pcie_configured = (io_sel == 2 || io_sel == 3 2469490a7f1SKumar Gala || io_sel == 5 || io_sel == 7); 2479490a7f1SKumar Gala 2489490a7f1SKumar Gala if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 2499490a7f1SKumar Gala printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", 2509490a7f1SKumar Gala pcie_ep ? "End Point" : "Root Complex", 2519490a7f1SKumar Gala (uint)pci); 2529490a7f1SKumar Gala if (pci->pme_msg_det) { 2539490a7f1SKumar Gala pci->pme_msg_det = 0xffffffff; 2549490a7f1SKumar Gala debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 2559490a7f1SKumar Gala } 2569490a7f1SKumar Gala printf ("\n"); 2579490a7f1SKumar Gala 2589490a7f1SKumar Gala /* inbound */ 2599490a7f1SKumar Gala pci_set_region(hose->regions + 0, 2606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI_MEMORY_BUS, 2616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI_MEMORY_PHYS, 2626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI_MEMORY_SIZE, 2639490a7f1SKumar Gala PCI_REGION_MEM | PCI_REGION_MEMORY); 2649490a7f1SKumar Gala 2659490a7f1SKumar Gala /* outbound memory */ 2669490a7f1SKumar Gala pci_set_region(hose->regions + 1, 2676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE1_MEM_BASE, 2686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE1_MEM_PHYS, 2696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE1_MEM_SIZE, 2709490a7f1SKumar Gala PCI_REGION_MEM); 2719490a7f1SKumar Gala 2729490a7f1SKumar Gala /* outbound io */ 2739490a7f1SKumar Gala pci_set_region(hose->regions + 2, 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE1_IO_BASE, 2756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE1_IO_PHYS, 2766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE1_IO_SIZE, 2779490a7f1SKumar Gala PCI_REGION_IO); 2789490a7f1SKumar Gala 2799490a7f1SKumar Gala hose->region_count = 3; 2806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_PCIE1_MEM_BASE2 2819490a7f1SKumar Gala /* outbound memory */ 2829490a7f1SKumar Gala pci_set_region(hose->regions + 3, 2836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE1_MEM_BASE2, 2846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE1_MEM_PHYS2, 2856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE1_MEM_SIZE2, 2869490a7f1SKumar Gala PCI_REGION_MEM); 2879490a7f1SKumar Gala hose->region_count++; 2889490a7f1SKumar Gala #endif 2899490a7f1SKumar Gala hose->first_busno=first_free_busno; 2909490a7f1SKumar Gala 2919490a7f1SKumar Gala pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 2929490a7f1SKumar Gala 2939490a7f1SKumar Gala fsl_pci_init(hose); 2949490a7f1SKumar Gala 2959490a7f1SKumar Gala first_free_busno=hose->last_busno+1; 2969490a7f1SKumar Gala printf(" PCIE1 on bus %02x - %02x\n", 2979490a7f1SKumar Gala hose->first_busno,hose->last_busno); 2989490a7f1SKumar Gala 2999490a7f1SKumar Gala } else { 3009490a7f1SKumar Gala printf (" PCIE1: disabled\n"); 3019490a7f1SKumar Gala } 3029490a7f1SKumar Gala 3039490a7f1SKumar Gala } 3049490a7f1SKumar Gala #else 3059490a7f1SKumar Gala gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 3069490a7f1SKumar Gala #endif 3079490a7f1SKumar Gala 3089490a7f1SKumar Gala #ifdef CONFIG_PCIE2 3099490a7f1SKumar Gala { 3106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 3119490a7f1SKumar Gala extern void fsl_pci_init(struct pci_controller *hose); 3129490a7f1SKumar Gala struct pci_controller *hose = &pcie2_hose; 3139490a7f1SKumar Gala int pcie_ep = (host_agent == 3); 3149490a7f1SKumar Gala int pcie_configured = (io_sel == 5 || io_sel == 7); 3159490a7f1SKumar Gala 3169490a7f1SKumar Gala if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 3179490a7f1SKumar Gala printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", 3189490a7f1SKumar Gala pcie_ep ? "End Point" : "Root Complex", 3199490a7f1SKumar Gala (uint)pci); 3209490a7f1SKumar Gala if (pci->pme_msg_det) { 3219490a7f1SKumar Gala pci->pme_msg_det = 0xffffffff; 3229490a7f1SKumar Gala debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 3239490a7f1SKumar Gala } 3249490a7f1SKumar Gala printf ("\n"); 3259490a7f1SKumar Gala 3269490a7f1SKumar Gala /* inbound */ 3279490a7f1SKumar Gala pci_set_region(hose->regions + 0, 3286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI_MEMORY_BUS, 3296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI_MEMORY_PHYS, 3306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI_MEMORY_SIZE, 3319490a7f1SKumar Gala PCI_REGION_MEM | PCI_REGION_MEMORY); 3329490a7f1SKumar Gala 3339490a7f1SKumar Gala /* outbound memory */ 3349490a7f1SKumar Gala pci_set_region(hose->regions + 1, 3356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE2_MEM_BASE, 3366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE2_MEM_PHYS, 3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE2_MEM_SIZE, 3389490a7f1SKumar Gala PCI_REGION_MEM); 3399490a7f1SKumar Gala 3409490a7f1SKumar Gala /* outbound io */ 3419490a7f1SKumar Gala pci_set_region(hose->regions + 2, 3426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE2_IO_BASE, 3436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE2_IO_PHYS, 3446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE2_IO_SIZE, 3459490a7f1SKumar Gala PCI_REGION_IO); 3469490a7f1SKumar Gala 3479490a7f1SKumar Gala hose->region_count = 3; 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_PCIE2_MEM_BASE2 3499490a7f1SKumar Gala /* outbound memory */ 3509490a7f1SKumar Gala pci_set_region(hose->regions + 3, 3516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE2_MEM_BASE2, 3526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE2_MEM_PHYS2, 3536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCIE2_MEM_SIZE2, 3549490a7f1SKumar Gala PCI_REGION_MEM); 3559490a7f1SKumar Gala hose->region_count++; 3569490a7f1SKumar Gala #endif 3579490a7f1SKumar Gala hose->first_busno=first_free_busno; 3589490a7f1SKumar Gala pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 3599490a7f1SKumar Gala 3609490a7f1SKumar Gala fsl_pci_init(hose); 3619490a7f1SKumar Gala first_free_busno=hose->last_busno+1; 3629490a7f1SKumar Gala printf (" PCIE2 on bus %02x - %02x\n", 3639490a7f1SKumar Gala hose->first_busno,hose->last_busno); 3649490a7f1SKumar Gala 3659490a7f1SKumar Gala } else { 3669490a7f1SKumar Gala printf (" PCIE2: disabled\n"); 3679490a7f1SKumar Gala } 3689490a7f1SKumar Gala 3699490a7f1SKumar Gala } 3709490a7f1SKumar Gala #else 3719490a7f1SKumar Gala gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 3729490a7f1SKumar Gala #endif 3739490a7f1SKumar Gala 3749490a7f1SKumar Gala 3759490a7f1SKumar Gala #ifdef CONFIG_PCI1 3769490a7f1SKumar Gala { 3776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 3789490a7f1SKumar Gala extern void fsl_pci_init(struct pci_controller *hose); 3799490a7f1SKumar Gala struct pci_controller *hose = &pci1_hose; 3809490a7f1SKumar Gala 3819490a7f1SKumar Gala uint pci_agent = (host_agent == 6); 3829490a7f1SKumar Gala uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 3839490a7f1SKumar Gala uint pci_32 = 1; 3849490a7f1SKumar Gala uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 3859490a7f1SKumar Gala uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 3869490a7f1SKumar Gala 3879490a7f1SKumar Gala 3889490a7f1SKumar Gala if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 3899490a7f1SKumar Gala printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 3909490a7f1SKumar Gala (pci_32) ? 32 : 64, 3919490a7f1SKumar Gala (pci_speed == 33333000) ? "33" : 3929490a7f1SKumar Gala (pci_speed == 66666000) ? "66" : "unknown", 3939490a7f1SKumar Gala pci_clk_sel ? "sync" : "async", 3949490a7f1SKumar Gala pci_agent ? "agent" : "host", 3959490a7f1SKumar Gala pci_arb ? "arbiter" : "external-arbiter", 3969490a7f1SKumar Gala (uint)pci 3979490a7f1SKumar Gala ); 3989490a7f1SKumar Gala 3999490a7f1SKumar Gala /* inbound */ 4009490a7f1SKumar Gala pci_set_region(hose->regions + 0, 4016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI_MEMORY_BUS, 4026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI_MEMORY_PHYS, 4036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI_MEMORY_SIZE, 4049490a7f1SKumar Gala PCI_REGION_MEM | PCI_REGION_MEMORY); 4059490a7f1SKumar Gala 4069490a7f1SKumar Gala /* outbound memory */ 4079490a7f1SKumar Gala pci_set_region(hose->regions + 1, 4086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI1_MEM_BASE, 4096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI1_MEM_PHYS, 4106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI1_MEM_SIZE, 4119490a7f1SKumar Gala PCI_REGION_MEM); 4129490a7f1SKumar Gala 4139490a7f1SKumar Gala /* outbound io */ 4149490a7f1SKumar Gala pci_set_region(hose->regions + 2, 4156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI1_IO_BASE, 4166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI1_IO_PHYS, 4176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI1_IO_SIZE, 4189490a7f1SKumar Gala PCI_REGION_IO); 4199490a7f1SKumar Gala hose->region_count = 3; 4206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_PCI1_MEM_BASE2 4219490a7f1SKumar Gala /* outbound memory */ 4229490a7f1SKumar Gala pci_set_region(hose->regions + 3, 4236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI1_MEM_BASE2, 4246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI1_MEM_PHYS2, 4256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_PCI1_MEM_SIZE2, 4269490a7f1SKumar Gala PCI_REGION_MEM); 4279490a7f1SKumar Gala hose->region_count++; 4289490a7f1SKumar Gala #endif 4299490a7f1SKumar Gala hose->first_busno=first_free_busno; 4309490a7f1SKumar Gala pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 4319490a7f1SKumar Gala 4329490a7f1SKumar Gala fsl_pci_init(hose); 4339490a7f1SKumar Gala first_free_busno=hose->last_busno+1; 4349490a7f1SKumar Gala printf ("PCI on bus %02x - %02x\n", 4359490a7f1SKumar Gala hose->first_busno,hose->last_busno); 4369490a7f1SKumar Gala } else { 4379490a7f1SKumar Gala printf (" PCI: disabled\n"); 4389490a7f1SKumar Gala } 4399490a7f1SKumar Gala } 4409490a7f1SKumar Gala #else 4419490a7f1SKumar Gala gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 4429490a7f1SKumar Gala #endif 4439490a7f1SKumar Gala } 4449490a7f1SKumar Gala 4459490a7f1SKumar Gala 4469490a7f1SKumar Gala int board_early_init_r(void) 4479490a7f1SKumar Gala { 4486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 4499490a7f1SKumar Gala const u8 flash_esel = 1; 4509490a7f1SKumar Gala 4519490a7f1SKumar Gala /* 4529490a7f1SKumar Gala * Remap Boot flash + PROMJET region to caching-inhibited 4539490a7f1SKumar Gala * so that flash can be erased properly. 4549490a7f1SKumar Gala */ 4559490a7f1SKumar Gala 4567c0d4a75SKumar Gala /* Flush d-cache and invalidate i-cache of any FLASH data */ 4577c0d4a75SKumar Gala flush_dcache(); 4587c0d4a75SKumar Gala invalidate_icache(); 4599490a7f1SKumar Gala 4609490a7f1SKumar Gala /* invalidate existing TLB entry for flash + promjet */ 4619490a7f1SKumar Gala disable_tlb(flash_esel); 4629490a7f1SKumar Gala 4639490a7f1SKumar Gala set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ 4649490a7f1SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 4659490a7f1SKumar Gala 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 4669490a7f1SKumar Gala 4679490a7f1SKumar Gala return 0; 4689490a7f1SKumar Gala } 4699490a7f1SKumar Gala 4709490a7f1SKumar Gala #ifdef CONFIG_GET_CLK_FROM_ICS307 4719490a7f1SKumar Gala /* decode S[0-2] to Output Divider (OD) */ 4729490a7f1SKumar Gala static unsigned char 4739490a7f1SKumar Gala ics307_S_to_OD[] = { 4749490a7f1SKumar Gala 10, 2, 8, 4, 5, 7, 3, 6 4759490a7f1SKumar Gala }; 4769490a7f1SKumar Gala 4779490a7f1SKumar Gala /* Calculate frequency being generated by ICS307-02 clock chip based upon 4789490a7f1SKumar Gala * the control bytes being programmed into it. */ 4799490a7f1SKumar Gala /* XXX: This function should probably go into a common library */ 4809490a7f1SKumar Gala static unsigned long 4819490a7f1SKumar Gala ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 4829490a7f1SKumar Gala { 4839490a7f1SKumar Gala const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 4849490a7f1SKumar Gala unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 4859490a7f1SKumar Gala unsigned long RDW = cw2 & 0x7F; 4869490a7f1SKumar Gala unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 4879490a7f1SKumar Gala unsigned long freq; 4889490a7f1SKumar Gala 4899490a7f1SKumar Gala /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 4909490a7f1SKumar Gala 4919490a7f1SKumar Gala /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 4929490a7f1SKumar Gala * cw1: V8 V7 V6 V5 V4 V3 V2 V1 4939490a7f1SKumar Gala * cw2: V0 R6 R5 R4 R3 R2 R1 R0 4949490a7f1SKumar Gala * 4959490a7f1SKumar Gala * R6:R0 = Reference Divider Word (RDW) 4969490a7f1SKumar Gala * V8:V0 = VCO Divider Word (VDW) 4979490a7f1SKumar Gala * S2:S0 = Output Divider Select (OD) 4989490a7f1SKumar Gala * F1:F0 = Function of CLK2 Output 4999490a7f1SKumar Gala * TTL = duty cycle 5009490a7f1SKumar Gala * C1:C0 = internal load capacitance for cyrstal 5019490a7f1SKumar Gala */ 5029490a7f1SKumar Gala 5039490a7f1SKumar Gala /* Adding 1 to get a "nicely" rounded number, but this needs 5049490a7f1SKumar Gala * more tweaking to get a "properly" rounded number. */ 5059490a7f1SKumar Gala 5069490a7f1SKumar Gala freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 5079490a7f1SKumar Gala 5089490a7f1SKumar Gala debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 5099490a7f1SKumar Gala freq); 5109490a7f1SKumar Gala return freq; 5119490a7f1SKumar Gala } 5129490a7f1SKumar Gala 5139490a7f1SKumar Gala unsigned long 5149490a7f1SKumar Gala get_board_sys_clk(ulong dummy) 5159490a7f1SKumar Gala { 5169490a7f1SKumar Gala return ics307_clk_freq ( 5179490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_VSYSCLK0), 5189490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_VSYSCLK1), 5199490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_VSYSCLK2) 5209490a7f1SKumar Gala ); 5219490a7f1SKumar Gala } 5229490a7f1SKumar Gala 5239490a7f1SKumar Gala unsigned long 5249490a7f1SKumar Gala get_board_ddr_clk(ulong dummy) 5259490a7f1SKumar Gala { 5269490a7f1SKumar Gala return ics307_clk_freq ( 5279490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_VDDRCLK0), 5289490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_VDDRCLK1), 5299490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_VDDRCLK2) 5309490a7f1SKumar Gala ); 5319490a7f1SKumar Gala } 5329490a7f1SKumar Gala #else 5339490a7f1SKumar Gala unsigned long 5349490a7f1SKumar Gala get_board_sys_clk(ulong dummy) 5359490a7f1SKumar Gala { 5369490a7f1SKumar Gala u8 i; 5379490a7f1SKumar Gala ulong val = 0; 5389490a7f1SKumar Gala 5399490a7f1SKumar Gala i = in8(PIXIS_BASE + PIXIS_SPD); 5409490a7f1SKumar Gala i &= 0x07; 5419490a7f1SKumar Gala 5429490a7f1SKumar Gala switch (i) { 5439490a7f1SKumar Gala case 0: 5449490a7f1SKumar Gala val = 33333333; 5459490a7f1SKumar Gala break; 5469490a7f1SKumar Gala case 1: 5479490a7f1SKumar Gala val = 40000000; 5489490a7f1SKumar Gala break; 5499490a7f1SKumar Gala case 2: 5509490a7f1SKumar Gala val = 50000000; 5519490a7f1SKumar Gala break; 5529490a7f1SKumar Gala case 3: 5539490a7f1SKumar Gala val = 66666666; 5549490a7f1SKumar Gala break; 5559490a7f1SKumar Gala case 4: 5569490a7f1SKumar Gala val = 83333333; 5579490a7f1SKumar Gala break; 5589490a7f1SKumar Gala case 5: 5599490a7f1SKumar Gala val = 100000000; 5609490a7f1SKumar Gala break; 5619490a7f1SKumar Gala case 6: 5629490a7f1SKumar Gala val = 133333333; 5639490a7f1SKumar Gala break; 5649490a7f1SKumar Gala case 7: 5659490a7f1SKumar Gala val = 166666666; 5669490a7f1SKumar Gala break; 5679490a7f1SKumar Gala } 5689490a7f1SKumar Gala 5699490a7f1SKumar Gala return val; 5709490a7f1SKumar Gala } 5719490a7f1SKumar Gala 5729490a7f1SKumar Gala unsigned long 5739490a7f1SKumar Gala get_board_ddr_clk(ulong dummy) 5749490a7f1SKumar Gala { 5759490a7f1SKumar Gala u8 i; 5769490a7f1SKumar Gala ulong val = 0; 5779490a7f1SKumar Gala 5789490a7f1SKumar Gala i = in8(PIXIS_BASE + PIXIS_SPD); 5799490a7f1SKumar Gala i &= 0x38; 5809490a7f1SKumar Gala i >>= 3; 5819490a7f1SKumar Gala 5829490a7f1SKumar Gala switch (i) { 5839490a7f1SKumar Gala case 0: 5849490a7f1SKumar Gala val = 33333333; 5859490a7f1SKumar Gala break; 5869490a7f1SKumar Gala case 1: 5879490a7f1SKumar Gala val = 40000000; 5889490a7f1SKumar Gala break; 5899490a7f1SKumar Gala case 2: 5909490a7f1SKumar Gala val = 50000000; 5919490a7f1SKumar Gala break; 5929490a7f1SKumar Gala case 3: 5939490a7f1SKumar Gala val = 66666666; 5949490a7f1SKumar Gala break; 5959490a7f1SKumar Gala case 4: 5969490a7f1SKumar Gala val = 83333333; 5979490a7f1SKumar Gala break; 5989490a7f1SKumar Gala case 5: 5999490a7f1SKumar Gala val = 100000000; 6009490a7f1SKumar Gala break; 6019490a7f1SKumar Gala case 6: 6029490a7f1SKumar Gala val = 133333333; 6039490a7f1SKumar Gala break; 6049490a7f1SKumar Gala case 7: 6059490a7f1SKumar Gala val = 166666666; 6069490a7f1SKumar Gala break; 6079490a7f1SKumar Gala } 6089490a7f1SKumar Gala return val; 6099490a7f1SKumar Gala } 6109490a7f1SKumar Gala #endif 6119490a7f1SKumar Gala 612374b9038SHeiko Schocher int is_sata_supported(void) 6130f8cbc18SJason Jin { 6146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 6150f8cbc18SJason Jin uint devdisr = gur->devdisr; 6160f8cbc18SJason Jin uint sdrs2_io_sel = 6170f8cbc18SJason Jin (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 6180f8cbc18SJason Jin if (sdrs2_io_sel & 0x04) 6190f8cbc18SJason Jin return 0; 6200f8cbc18SJason Jin 6210f8cbc18SJason Jin return 1; 6220f8cbc18SJason Jin } 6230f8cbc18SJason Jin 624*2e26d837SJason Jin int board_eth_init(bd_t *bis) 625*2e26d837SJason Jin { 626*2e26d837SJason Jin #ifdef CONFIG_TSEC_ENET 627*2e26d837SJason Jin struct tsec_info_struct tsec_info[2]; 628*2e26d837SJason Jin volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 629*2e26d837SJason Jin int num = 0; 630*2e26d837SJason Jin uint sdrs2_io_sel = 631*2e26d837SJason Jin (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 632*2e26d837SJason Jin 633*2e26d837SJason Jin #ifdef CONFIG_TSEC1 634*2e26d837SJason Jin SET_STD_TSEC_INFO(tsec_info[num], 1); 635*2e26d837SJason Jin if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { 636*2e26d837SJason Jin tsec_info[num].phyaddr = 0; 637*2e26d837SJason Jin tsec_info[num].flags |= TSEC_SGMII; 638*2e26d837SJason Jin } 639*2e26d837SJason Jin num++; 640*2e26d837SJason Jin #endif 641*2e26d837SJason Jin #ifdef CONFIG_TSEC3 642*2e26d837SJason Jin SET_STD_TSEC_INFO(tsec_info[num], 3); 643*2e26d837SJason Jin if (sdrs2_io_sel == 4) { 644*2e26d837SJason Jin tsec_info[num].phyaddr = 1; 645*2e26d837SJason Jin tsec_info[num].flags |= TSEC_SGMII; 646*2e26d837SJason Jin } 647*2e26d837SJason Jin num++; 648*2e26d837SJason Jin #endif 649*2e26d837SJason Jin 650*2e26d837SJason Jin if (!num) { 651*2e26d837SJason Jin printf("No TSECs initialized\n"); 652*2e26d837SJason Jin return 0; 653*2e26d837SJason Jin } 654*2e26d837SJason Jin 655*2e26d837SJason Jin if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) 656*2e26d837SJason Jin fsl_sgmii_riser_init(tsec_info, num); 657*2e26d837SJason Jin 658*2e26d837SJason Jin tsec_eth_init(bis, tsec_info, num); 659*2e26d837SJason Jin #endif 660*2e26d837SJason Jin return pci_eth_init(bis); 661*2e26d837SJason Jin } 662*2e26d837SJason Jin 6639490a7f1SKumar Gala #if defined(CONFIG_OF_BOARD_SETUP) 6649490a7f1SKumar Gala void 6659490a7f1SKumar Gala ft_board_setup(void *blob, bd_t *bd) 6669490a7f1SKumar Gala { 6679490a7f1SKumar Gala int node, tmp[2]; 6689490a7f1SKumar Gala const char *path; 6699490a7f1SKumar Gala 6709490a7f1SKumar Gala ft_cpu_setup(blob, bd); 6719490a7f1SKumar Gala 6729490a7f1SKumar Gala node = fdt_path_offset(blob, "/aliases"); 6739490a7f1SKumar Gala tmp[0] = 0; 6749490a7f1SKumar Gala if (node >= 0) { 6759490a7f1SKumar Gala #ifdef CONFIG_PCI1 6769490a7f1SKumar Gala path = fdt_getprop(blob, node, "pci0", NULL); 6779490a7f1SKumar Gala if (path) { 6789490a7f1SKumar Gala tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 6799490a7f1SKumar Gala do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 6809490a7f1SKumar Gala } 6819490a7f1SKumar Gala #endif 6829490a7f1SKumar Gala #ifdef CONFIG_PCIE2 6839490a7f1SKumar Gala path = fdt_getprop(blob, node, "pci1", NULL); 6849490a7f1SKumar Gala if (path) { 6859490a7f1SKumar Gala tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; 6869490a7f1SKumar Gala do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 6879490a7f1SKumar Gala } 6889490a7f1SKumar Gala #endif 6899490a7f1SKumar Gala #ifdef CONFIG_PCIE1 6909490a7f1SKumar Gala path = fdt_getprop(blob, node, "pci2", NULL); 6919490a7f1SKumar Gala if (path) { 6929490a7f1SKumar Gala tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 6939490a7f1SKumar Gala do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 6949490a7f1SKumar Gala } 6959490a7f1SKumar Gala #endif 6969490a7f1SKumar Gala #ifdef CONFIG_PCIE3 6979490a7f1SKumar Gala path = fdt_getprop(blob, node, "pci3", NULL); 6989490a7f1SKumar Gala if (path) { 6999490a7f1SKumar Gala tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; 7009490a7f1SKumar Gala do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 7019490a7f1SKumar Gala } 7029490a7f1SKumar Gala #endif 7039490a7f1SKumar Gala } 7049490a7f1SKumar Gala } 7059490a7f1SKumar Gala #endif 706