19490a7f1SKumar Gala /* 29490a7f1SKumar Gala * Copyright 2008 Freescale Semiconductor. 39490a7f1SKumar Gala * 49490a7f1SKumar Gala * See file CREDITS for list of people who contributed to this 59490a7f1SKumar Gala * project. 69490a7f1SKumar Gala * 79490a7f1SKumar Gala * This program is free software; you can redistribute it and/or 89490a7f1SKumar Gala * modify it under the terms of the GNU General Public License as 99490a7f1SKumar Gala * published by the Free Software Foundation; either version 2 of 109490a7f1SKumar Gala * the License, or (at your option) any later version. 119490a7f1SKumar Gala * 129490a7f1SKumar Gala * This program is distributed in the hope that it will be useful, 139490a7f1SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 149490a7f1SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 159490a7f1SKumar Gala * GNU General Public License for more details. 169490a7f1SKumar Gala * 179490a7f1SKumar Gala * You should have received a copy of the GNU General Public License 189490a7f1SKumar Gala * along with this program; if not, write to the Free Software 199490a7f1SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 209490a7f1SKumar Gala * MA 02111-1307 USA 219490a7f1SKumar Gala */ 229490a7f1SKumar Gala 239490a7f1SKumar Gala #include <common.h> 249490a7f1SKumar Gala #include <command.h> 259490a7f1SKumar Gala #include <pci.h> 269490a7f1SKumar Gala #include <asm/processor.h> 279490a7f1SKumar Gala #include <asm/mmu.h> 289490a7f1SKumar Gala #include <asm/immap_85xx.h> 299490a7f1SKumar Gala #include <asm/immap_fsl_pci.h> 309490a7f1SKumar Gala #include <asm/fsl_ddr_sdram.h> 319490a7f1SKumar Gala #include <asm/io.h> 329490a7f1SKumar Gala #include <spd.h> 339490a7f1SKumar Gala #include <miiphy.h> 349490a7f1SKumar Gala #include <libfdt.h> 359490a7f1SKumar Gala #include <spd_sdram.h> 369490a7f1SKumar Gala #include <fdt_support.h> 379490a7f1SKumar Gala 389490a7f1SKumar Gala #include "../common/pixis.h" 399490a7f1SKumar Gala 409490a7f1SKumar Gala #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 419490a7f1SKumar Gala extern void ddr_enable_ecc(unsigned int dram_size); 429490a7f1SKumar Gala #endif 439490a7f1SKumar Gala 449490a7f1SKumar Gala phys_size_t fixed_sdram(void); 459490a7f1SKumar Gala 469490a7f1SKumar Gala int checkboard (void) 479490a7f1SKumar Gala { 489490a7f1SKumar Gala printf ("Board: MPC8536DS, System ID: 0x%02x, " 499490a7f1SKumar Gala "System Version: 0x%02x, FPGA Version: 0x%02x\n", 509490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 519490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_PVER)); 529490a7f1SKumar Gala return 0; 539490a7f1SKumar Gala } 549490a7f1SKumar Gala 559490a7f1SKumar Gala phys_size_t 569490a7f1SKumar Gala initdram(int board_type) 579490a7f1SKumar Gala { 589490a7f1SKumar Gala phys_size_t dram_size = 0; 599490a7f1SKumar Gala 609490a7f1SKumar Gala puts("Initializing...."); 619490a7f1SKumar Gala 629490a7f1SKumar Gala #ifdef CONFIG_SPD_EEPROM 639490a7f1SKumar Gala dram_size = fsl_ddr_sdram(); 649490a7f1SKumar Gala 659490a7f1SKumar Gala dram_size = setup_ddr_tlbs(dram_size / 0x100000); 669490a7f1SKumar Gala 679490a7f1SKumar Gala dram_size *= 0x100000; 689490a7f1SKumar Gala #else 699490a7f1SKumar Gala dram_size = fixed_sdram(); 709490a7f1SKumar Gala #endif 719490a7f1SKumar Gala 729490a7f1SKumar Gala #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 739490a7f1SKumar Gala /* 749490a7f1SKumar Gala * Initialize and enable DDR ECC. 759490a7f1SKumar Gala */ 769490a7f1SKumar Gala ddr_enable_ecc(dram_size); 779490a7f1SKumar Gala #endif 789490a7f1SKumar Gala puts(" DDR: "); 799490a7f1SKumar Gala return dram_size; 809490a7f1SKumar Gala } 819490a7f1SKumar Gala 829490a7f1SKumar Gala #if !defined(CONFIG_SPD_EEPROM) 839490a7f1SKumar Gala /* 849490a7f1SKumar Gala * Fixed sdram init -- doesn't use serial presence detect. 859490a7f1SKumar Gala */ 869490a7f1SKumar Gala 879490a7f1SKumar Gala phys_size_t fixed_sdram (void) 889490a7f1SKumar Gala { 899490a7f1SKumar Gala volatile immap_t *immap = (immap_t *)CFG_IMMR; 909490a7f1SKumar Gala volatile ccsr_ddr_t *ddr= &immap->im_ddr; 919490a7f1SKumar Gala uint d_init; 929490a7f1SKumar Gala 939490a7f1SKumar Gala ddr->cs0_bnds = CFG_DDR_CS0_BNDS; 949490a7f1SKumar Gala ddr->cs0_config = CFG_DDR_CS0_CONFIG; 959490a7f1SKumar Gala 969490a7f1SKumar Gala ddr->timing_cfg_3 = CFG_DDR_TIMING_3; 979490a7f1SKumar Gala ddr->timing_cfg_0 = CFG_DDR_TIMING_0; 989490a7f1SKumar Gala ddr->timing_cfg_1 = CFG_DDR_TIMING_1; 999490a7f1SKumar Gala ddr->timing_cfg_2 = CFG_DDR_TIMING_2; 1009490a7f1SKumar Gala ddr->sdram_mode = CFG_DDR_MODE_1; 1019490a7f1SKumar Gala ddr->sdram_mode_2 = CFG_DDR_MODE_2; 1029490a7f1SKumar Gala ddr->sdram_interval = CFG_DDR_INTERVAL; 1039490a7f1SKumar Gala ddr->sdram_data_init = CFG_DDR_DATA_INIT; 1049490a7f1SKumar Gala ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; 1059490a7f1SKumar Gala ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; 1069490a7f1SKumar Gala 1079490a7f1SKumar Gala #if defined (CONFIG_DDR_ECC) 1089490a7f1SKumar Gala ddr->err_int_en = CFG_DDR_ERR_INT_EN; 1099490a7f1SKumar Gala ddr->err_disable = CFG_DDR_ERR_DIS; 1109490a7f1SKumar Gala ddr->err_sbe = CFG_DDR_SBE; 1119490a7f1SKumar Gala #endif 1129490a7f1SKumar Gala asm("sync;isync"); 1139490a7f1SKumar Gala 1149490a7f1SKumar Gala udelay(500); 1159490a7f1SKumar Gala 1169490a7f1SKumar Gala ddr->sdram_cfg = CFG_DDR_CONTROL; 1179490a7f1SKumar Gala 1189490a7f1SKumar Gala #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 1199490a7f1SKumar Gala d_init = 1; 1209490a7f1SKumar Gala debug("DDR - 1st controller: memory initializing\n"); 1219490a7f1SKumar Gala /* 1229490a7f1SKumar Gala * Poll until memory is initialized. 1239490a7f1SKumar Gala * 512 Meg at 400 might hit this 200 times or so. 1249490a7f1SKumar Gala */ 1259490a7f1SKumar Gala while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 1269490a7f1SKumar Gala udelay(1000); 1279490a7f1SKumar Gala } 1289490a7f1SKumar Gala debug("DDR: memory initialized\n\n"); 1299490a7f1SKumar Gala asm("sync; isync"); 1309490a7f1SKumar Gala udelay(500); 1319490a7f1SKumar Gala #endif 1329490a7f1SKumar Gala 1339490a7f1SKumar Gala return 512 * 1024 * 1024; 1349490a7f1SKumar Gala } 1359490a7f1SKumar Gala 1369490a7f1SKumar Gala #endif 1379490a7f1SKumar Gala 1389490a7f1SKumar Gala #ifdef CONFIG_PCI1 1399490a7f1SKumar Gala static struct pci_controller pci1_hose; 1409490a7f1SKumar Gala #endif 1419490a7f1SKumar Gala 1429490a7f1SKumar Gala #ifdef CONFIG_PCIE1 1439490a7f1SKumar Gala static struct pci_controller pcie1_hose; 1449490a7f1SKumar Gala #endif 1459490a7f1SKumar Gala 1469490a7f1SKumar Gala #ifdef CONFIG_PCIE2 1479490a7f1SKumar Gala static struct pci_controller pcie2_hose; 1489490a7f1SKumar Gala #endif 1499490a7f1SKumar Gala 1509490a7f1SKumar Gala #ifdef CONFIG_PCIE3 1519490a7f1SKumar Gala static struct pci_controller pcie3_hose; 1529490a7f1SKumar Gala #endif 1539490a7f1SKumar Gala 1549490a7f1SKumar Gala int first_free_busno=0; 1559490a7f1SKumar Gala 1569490a7f1SKumar Gala void 1579490a7f1SKumar Gala pci_init_board(void) 1589490a7f1SKumar Gala { 1599490a7f1SKumar Gala volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 1609490a7f1SKumar Gala uint devdisr = gur->devdisr; 1619490a7f1SKumar Gala uint sdrs2_io_sel = 1629490a7f1SKumar Gala (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 1639490a7f1SKumar Gala uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 1649490a7f1SKumar Gala uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 1659490a7f1SKumar Gala 1669490a7f1SKumar Gala debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ 1679490a7f1SKumar Gala host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); 1689490a7f1SKumar Gala 1699490a7f1SKumar Gala if (sdrs2_io_sel == 7) 1709490a7f1SKumar Gala printf(" Serdes2 disalbed\n"); 1719490a7f1SKumar Gala else if (sdrs2_io_sel == 4) { 1729490a7f1SKumar Gala printf(" eTSEC1 is in sgmii mode.\n"); 1739490a7f1SKumar Gala printf(" eTSEC3 is in sgmii mode.\n"); 1749490a7f1SKumar Gala } else if (sdrs2_io_sel == 6) 1759490a7f1SKumar Gala printf(" eTSEC1 is in sgmii mode.\n"); 1769490a7f1SKumar Gala 1779490a7f1SKumar Gala #ifdef CONFIG_PCIE3 1789490a7f1SKumar Gala { 1799490a7f1SKumar Gala volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; 1809490a7f1SKumar Gala extern void fsl_pci_init(struct pci_controller *hose); 1819490a7f1SKumar Gala struct pci_controller *hose = &pcie3_hose; 1829490a7f1SKumar Gala int pcie_ep = (host_agent == 1); 1839490a7f1SKumar Gala int pcie_configured = (io_sel == 7); 1849490a7f1SKumar Gala 1859490a7f1SKumar Gala if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 1869490a7f1SKumar Gala printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", 1879490a7f1SKumar Gala pcie_ep ? "End Point" : "Root Complex", 1889490a7f1SKumar Gala (uint)pci); 1899490a7f1SKumar Gala if (pci->pme_msg_det) { 1909490a7f1SKumar Gala pci->pme_msg_det = 0xffffffff; 1919490a7f1SKumar Gala debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 1929490a7f1SKumar Gala } 1939490a7f1SKumar Gala printf ("\n"); 1949490a7f1SKumar Gala 1959490a7f1SKumar Gala /* inbound */ 1969490a7f1SKumar Gala pci_set_region(hose->regions + 0, 1979490a7f1SKumar Gala CFG_PCI_MEMORY_BUS, 1989490a7f1SKumar Gala CFG_PCI_MEMORY_PHYS, 1999490a7f1SKumar Gala CFG_PCI_MEMORY_SIZE, 2009490a7f1SKumar Gala PCI_REGION_MEM | PCI_REGION_MEMORY); 2019490a7f1SKumar Gala 2029490a7f1SKumar Gala /* outbound memory */ 2039490a7f1SKumar Gala pci_set_region(hose->regions + 1, 2049490a7f1SKumar Gala CFG_PCIE3_MEM_BASE, 2059490a7f1SKumar Gala CFG_PCIE3_MEM_PHYS, 2069490a7f1SKumar Gala CFG_PCIE3_MEM_SIZE, 2079490a7f1SKumar Gala PCI_REGION_MEM); 2089490a7f1SKumar Gala 2099490a7f1SKumar Gala /* outbound io */ 2109490a7f1SKumar Gala pci_set_region(hose->regions + 2, 2119490a7f1SKumar Gala CFG_PCIE3_IO_BASE, 2129490a7f1SKumar Gala CFG_PCIE3_IO_PHYS, 2139490a7f1SKumar Gala CFG_PCIE3_IO_SIZE, 2149490a7f1SKumar Gala PCI_REGION_IO); 2159490a7f1SKumar Gala 2169490a7f1SKumar Gala hose->region_count = 3; 2179490a7f1SKumar Gala 2189490a7f1SKumar Gala hose->first_busno=first_free_busno; 2199490a7f1SKumar Gala pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 2209490a7f1SKumar Gala 2219490a7f1SKumar Gala fsl_pci_init(hose); 2229490a7f1SKumar Gala 2239490a7f1SKumar Gala first_free_busno=hose->last_busno+1; 2249490a7f1SKumar Gala printf (" PCIE3 on bus %02x - %02x\n", 2259490a7f1SKumar Gala hose->first_busno,hose->last_busno); 2269490a7f1SKumar Gala } else { 2279490a7f1SKumar Gala printf (" PCIE3: disabled\n"); 2289490a7f1SKumar Gala } 2299490a7f1SKumar Gala 2309490a7f1SKumar Gala } 2319490a7f1SKumar Gala #else 2329490a7f1SKumar Gala gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 2339490a7f1SKumar Gala #endif 2349490a7f1SKumar Gala 2359490a7f1SKumar Gala #ifdef CONFIG_PCIE1 2369490a7f1SKumar Gala { 2379490a7f1SKumar Gala volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 2389490a7f1SKumar Gala extern void fsl_pci_init(struct pci_controller *hose); 2399490a7f1SKumar Gala struct pci_controller *hose = &pcie1_hose; 2409490a7f1SKumar Gala int pcie_ep = (host_agent == 5); 2419490a7f1SKumar Gala int pcie_configured = (io_sel == 2 || io_sel == 3 2429490a7f1SKumar Gala || io_sel == 5 || io_sel == 7); 2439490a7f1SKumar Gala 2449490a7f1SKumar Gala if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 2459490a7f1SKumar Gala printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", 2469490a7f1SKumar Gala pcie_ep ? "End Point" : "Root Complex", 2479490a7f1SKumar Gala (uint)pci); 2489490a7f1SKumar Gala if (pci->pme_msg_det) { 2499490a7f1SKumar Gala pci->pme_msg_det = 0xffffffff; 2509490a7f1SKumar Gala debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 2519490a7f1SKumar Gala } 2529490a7f1SKumar Gala printf ("\n"); 2539490a7f1SKumar Gala 2549490a7f1SKumar Gala /* inbound */ 2559490a7f1SKumar Gala pci_set_region(hose->regions + 0, 2569490a7f1SKumar Gala CFG_PCI_MEMORY_BUS, 2579490a7f1SKumar Gala CFG_PCI_MEMORY_PHYS, 2589490a7f1SKumar Gala CFG_PCI_MEMORY_SIZE, 2599490a7f1SKumar Gala PCI_REGION_MEM | PCI_REGION_MEMORY); 2609490a7f1SKumar Gala 2619490a7f1SKumar Gala /* outbound memory */ 2629490a7f1SKumar Gala pci_set_region(hose->regions + 1, 2639490a7f1SKumar Gala CFG_PCIE1_MEM_BASE, 2649490a7f1SKumar Gala CFG_PCIE1_MEM_PHYS, 2659490a7f1SKumar Gala CFG_PCIE1_MEM_SIZE, 2669490a7f1SKumar Gala PCI_REGION_MEM); 2679490a7f1SKumar Gala 2689490a7f1SKumar Gala /* outbound io */ 2699490a7f1SKumar Gala pci_set_region(hose->regions + 2, 2709490a7f1SKumar Gala CFG_PCIE1_IO_BASE, 2719490a7f1SKumar Gala CFG_PCIE1_IO_PHYS, 2729490a7f1SKumar Gala CFG_PCIE1_IO_SIZE, 2739490a7f1SKumar Gala PCI_REGION_IO); 2749490a7f1SKumar Gala 2759490a7f1SKumar Gala hose->region_count = 3; 2769490a7f1SKumar Gala #ifdef CFG_PCIE1_MEM_BASE2 2779490a7f1SKumar Gala /* outbound memory */ 2789490a7f1SKumar Gala pci_set_region(hose->regions + 3, 2799490a7f1SKumar Gala CFG_PCIE1_MEM_BASE2, 2809490a7f1SKumar Gala CFG_PCIE1_MEM_PHYS2, 2819490a7f1SKumar Gala CFG_PCIE1_MEM_SIZE2, 2829490a7f1SKumar Gala PCI_REGION_MEM); 2839490a7f1SKumar Gala hose->region_count++; 2849490a7f1SKumar Gala #endif 2859490a7f1SKumar Gala hose->first_busno=first_free_busno; 2869490a7f1SKumar Gala 2879490a7f1SKumar Gala pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 2889490a7f1SKumar Gala 2899490a7f1SKumar Gala fsl_pci_init(hose); 2909490a7f1SKumar Gala 2919490a7f1SKumar Gala first_free_busno=hose->last_busno+1; 2929490a7f1SKumar Gala printf(" PCIE1 on bus %02x - %02x\n", 2939490a7f1SKumar Gala hose->first_busno,hose->last_busno); 2949490a7f1SKumar Gala 2959490a7f1SKumar Gala } else { 2969490a7f1SKumar Gala printf (" PCIE1: disabled\n"); 2979490a7f1SKumar Gala } 2989490a7f1SKumar Gala 2999490a7f1SKumar Gala } 3009490a7f1SKumar Gala #else 3019490a7f1SKumar Gala gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 3029490a7f1SKumar Gala #endif 3039490a7f1SKumar Gala 3049490a7f1SKumar Gala #ifdef CONFIG_PCIE2 3059490a7f1SKumar Gala { 3069490a7f1SKumar Gala volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; 3079490a7f1SKumar Gala extern void fsl_pci_init(struct pci_controller *hose); 3089490a7f1SKumar Gala struct pci_controller *hose = &pcie2_hose; 3099490a7f1SKumar Gala int pcie_ep = (host_agent == 3); 3109490a7f1SKumar Gala int pcie_configured = (io_sel == 5 || io_sel == 7); 3119490a7f1SKumar Gala 3129490a7f1SKumar Gala if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 3139490a7f1SKumar Gala printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", 3149490a7f1SKumar Gala pcie_ep ? "End Point" : "Root Complex", 3159490a7f1SKumar Gala (uint)pci); 3169490a7f1SKumar Gala if (pci->pme_msg_det) { 3179490a7f1SKumar Gala pci->pme_msg_det = 0xffffffff; 3189490a7f1SKumar Gala debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 3199490a7f1SKumar Gala } 3209490a7f1SKumar Gala printf ("\n"); 3219490a7f1SKumar Gala 3229490a7f1SKumar Gala /* inbound */ 3239490a7f1SKumar Gala pci_set_region(hose->regions + 0, 3249490a7f1SKumar Gala CFG_PCI_MEMORY_BUS, 3259490a7f1SKumar Gala CFG_PCI_MEMORY_PHYS, 3269490a7f1SKumar Gala CFG_PCI_MEMORY_SIZE, 3279490a7f1SKumar Gala PCI_REGION_MEM | PCI_REGION_MEMORY); 3289490a7f1SKumar Gala 3299490a7f1SKumar Gala /* outbound memory */ 3309490a7f1SKumar Gala pci_set_region(hose->regions + 1, 3319490a7f1SKumar Gala CFG_PCIE2_MEM_BASE, 3329490a7f1SKumar Gala CFG_PCIE2_MEM_PHYS, 3339490a7f1SKumar Gala CFG_PCIE2_MEM_SIZE, 3349490a7f1SKumar Gala PCI_REGION_MEM); 3359490a7f1SKumar Gala 3369490a7f1SKumar Gala /* outbound io */ 3379490a7f1SKumar Gala pci_set_region(hose->regions + 2, 3389490a7f1SKumar Gala CFG_PCIE2_IO_BASE, 3399490a7f1SKumar Gala CFG_PCIE2_IO_PHYS, 3409490a7f1SKumar Gala CFG_PCIE2_IO_SIZE, 3419490a7f1SKumar Gala PCI_REGION_IO); 3429490a7f1SKumar Gala 3439490a7f1SKumar Gala hose->region_count = 3; 3449490a7f1SKumar Gala #ifdef CFG_PCIE2_MEM_BASE2 3459490a7f1SKumar Gala /* outbound memory */ 3469490a7f1SKumar Gala pci_set_region(hose->regions + 3, 3479490a7f1SKumar Gala CFG_PCIE2_MEM_BASE2, 3489490a7f1SKumar Gala CFG_PCIE2_MEM_PHYS2, 3499490a7f1SKumar Gala CFG_PCIE2_MEM_SIZE2, 3509490a7f1SKumar Gala PCI_REGION_MEM); 3519490a7f1SKumar Gala hose->region_count++; 3529490a7f1SKumar Gala #endif 3539490a7f1SKumar Gala hose->first_busno=first_free_busno; 3549490a7f1SKumar Gala pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 3559490a7f1SKumar Gala 3569490a7f1SKumar Gala fsl_pci_init(hose); 3579490a7f1SKumar Gala first_free_busno=hose->last_busno+1; 3589490a7f1SKumar Gala printf (" PCIE2 on bus %02x - %02x\n", 3599490a7f1SKumar Gala hose->first_busno,hose->last_busno); 3609490a7f1SKumar Gala 3619490a7f1SKumar Gala } else { 3629490a7f1SKumar Gala printf (" PCIE2: disabled\n"); 3639490a7f1SKumar Gala } 3649490a7f1SKumar Gala 3659490a7f1SKumar Gala } 3669490a7f1SKumar Gala #else 3679490a7f1SKumar Gala gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 3689490a7f1SKumar Gala #endif 3699490a7f1SKumar Gala 3709490a7f1SKumar Gala 3719490a7f1SKumar Gala #ifdef CONFIG_PCI1 3729490a7f1SKumar Gala { 3739490a7f1SKumar Gala volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 3749490a7f1SKumar Gala extern void fsl_pci_init(struct pci_controller *hose); 3759490a7f1SKumar Gala struct pci_controller *hose = &pci1_hose; 3769490a7f1SKumar Gala 3779490a7f1SKumar Gala uint pci_agent = (host_agent == 6); 3789490a7f1SKumar Gala uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 3799490a7f1SKumar Gala uint pci_32 = 1; 3809490a7f1SKumar Gala uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 3819490a7f1SKumar Gala uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 3829490a7f1SKumar Gala 3839490a7f1SKumar Gala 3849490a7f1SKumar Gala if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 3859490a7f1SKumar Gala printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 3869490a7f1SKumar Gala (pci_32) ? 32 : 64, 3879490a7f1SKumar Gala (pci_speed == 33333000) ? "33" : 3889490a7f1SKumar Gala (pci_speed == 66666000) ? "66" : "unknown", 3899490a7f1SKumar Gala pci_clk_sel ? "sync" : "async", 3909490a7f1SKumar Gala pci_agent ? "agent" : "host", 3919490a7f1SKumar Gala pci_arb ? "arbiter" : "external-arbiter", 3929490a7f1SKumar Gala (uint)pci 3939490a7f1SKumar Gala ); 3949490a7f1SKumar Gala 3959490a7f1SKumar Gala /* inbound */ 3969490a7f1SKumar Gala pci_set_region(hose->regions + 0, 3979490a7f1SKumar Gala CFG_PCI_MEMORY_BUS, 3989490a7f1SKumar Gala CFG_PCI_MEMORY_PHYS, 3999490a7f1SKumar Gala CFG_PCI_MEMORY_SIZE, 4009490a7f1SKumar Gala PCI_REGION_MEM | PCI_REGION_MEMORY); 4019490a7f1SKumar Gala 4029490a7f1SKumar Gala /* outbound memory */ 4039490a7f1SKumar Gala pci_set_region(hose->regions + 1, 4049490a7f1SKumar Gala CFG_PCI1_MEM_BASE, 4059490a7f1SKumar Gala CFG_PCI1_MEM_PHYS, 4069490a7f1SKumar Gala CFG_PCI1_MEM_SIZE, 4079490a7f1SKumar Gala PCI_REGION_MEM); 4089490a7f1SKumar Gala 4099490a7f1SKumar Gala /* outbound io */ 4109490a7f1SKumar Gala pci_set_region(hose->regions + 2, 4119490a7f1SKumar Gala CFG_PCI1_IO_BASE, 4129490a7f1SKumar Gala CFG_PCI1_IO_PHYS, 4139490a7f1SKumar Gala CFG_PCI1_IO_SIZE, 4149490a7f1SKumar Gala PCI_REGION_IO); 4159490a7f1SKumar Gala hose->region_count = 3; 4169490a7f1SKumar Gala #ifdef CFG_PCI1_MEM_BASE2 4179490a7f1SKumar Gala /* outbound memory */ 4189490a7f1SKumar Gala pci_set_region(hose->regions + 3, 4199490a7f1SKumar Gala CFG_PCI1_MEM_BASE2, 4209490a7f1SKumar Gala CFG_PCI1_MEM_PHYS2, 4219490a7f1SKumar Gala CFG_PCI1_MEM_SIZE2, 4229490a7f1SKumar Gala PCI_REGION_MEM); 4239490a7f1SKumar Gala hose->region_count++; 4249490a7f1SKumar Gala #endif 4259490a7f1SKumar Gala hose->first_busno=first_free_busno; 4269490a7f1SKumar Gala pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 4279490a7f1SKumar Gala 4289490a7f1SKumar Gala fsl_pci_init(hose); 4299490a7f1SKumar Gala first_free_busno=hose->last_busno+1; 4309490a7f1SKumar Gala printf ("PCI on bus %02x - %02x\n", 4319490a7f1SKumar Gala hose->first_busno,hose->last_busno); 4329490a7f1SKumar Gala } else { 4339490a7f1SKumar Gala printf (" PCI: disabled\n"); 4349490a7f1SKumar Gala } 4359490a7f1SKumar Gala } 4369490a7f1SKumar Gala #else 4379490a7f1SKumar Gala gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 4389490a7f1SKumar Gala #endif 4399490a7f1SKumar Gala } 4409490a7f1SKumar Gala 4419490a7f1SKumar Gala 4429490a7f1SKumar Gala int board_early_init_r(void) 4439490a7f1SKumar Gala { 4449490a7f1SKumar Gala unsigned int i; 4459490a7f1SKumar Gala const unsigned int flashbase = CFG_FLASH_BASE; 4469490a7f1SKumar Gala const u8 flash_esel = 1; 4479490a7f1SKumar Gala 4489490a7f1SKumar Gala /* 4499490a7f1SKumar Gala * Remap Boot flash + PROMJET region to caching-inhibited 4509490a7f1SKumar Gala * so that flash can be erased properly. 4519490a7f1SKumar Gala */ 4529490a7f1SKumar Gala 4539490a7f1SKumar Gala /* Invalidate any remaining lines of the flash from caches. */ 4549490a7f1SKumar Gala for (i = 0; i < 256*1024*1024; i+=32) { 4559490a7f1SKumar Gala asm volatile ("dcbi %0,%1": : "b" (flashbase), "r" (i)); 4569490a7f1SKumar Gala asm volatile ("icbi %0,%1": : "b" (flashbase), "r" (i)); 4579490a7f1SKumar Gala } 4589490a7f1SKumar Gala 4599490a7f1SKumar Gala /* invalidate existing TLB entry for flash + promjet */ 4609490a7f1SKumar Gala disable_tlb(flash_esel); 4619490a7f1SKumar Gala 4629490a7f1SKumar Gala set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ 4639490a7f1SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 4649490a7f1SKumar Gala 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 4659490a7f1SKumar Gala 4669490a7f1SKumar Gala return 0; 4679490a7f1SKumar Gala } 4689490a7f1SKumar Gala 4699490a7f1SKumar Gala #ifdef CONFIG_GET_CLK_FROM_ICS307 4709490a7f1SKumar Gala /* decode S[0-2] to Output Divider (OD) */ 4719490a7f1SKumar Gala static unsigned char 4729490a7f1SKumar Gala ics307_S_to_OD[] = { 4739490a7f1SKumar Gala 10, 2, 8, 4, 5, 7, 3, 6 4749490a7f1SKumar Gala }; 4759490a7f1SKumar Gala 4769490a7f1SKumar Gala /* Calculate frequency being generated by ICS307-02 clock chip based upon 4779490a7f1SKumar Gala * the control bytes being programmed into it. */ 4789490a7f1SKumar Gala /* XXX: This function should probably go into a common library */ 4799490a7f1SKumar Gala static unsigned long 4809490a7f1SKumar Gala ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 4819490a7f1SKumar Gala { 4829490a7f1SKumar Gala const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 4839490a7f1SKumar Gala unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 4849490a7f1SKumar Gala unsigned long RDW = cw2 & 0x7F; 4859490a7f1SKumar Gala unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 4869490a7f1SKumar Gala unsigned long freq; 4879490a7f1SKumar Gala 4889490a7f1SKumar Gala /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 4899490a7f1SKumar Gala 4909490a7f1SKumar Gala /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 4919490a7f1SKumar Gala * cw1: V8 V7 V6 V5 V4 V3 V2 V1 4929490a7f1SKumar Gala * cw2: V0 R6 R5 R4 R3 R2 R1 R0 4939490a7f1SKumar Gala * 4949490a7f1SKumar Gala * R6:R0 = Reference Divider Word (RDW) 4959490a7f1SKumar Gala * V8:V0 = VCO Divider Word (VDW) 4969490a7f1SKumar Gala * S2:S0 = Output Divider Select (OD) 4979490a7f1SKumar Gala * F1:F0 = Function of CLK2 Output 4989490a7f1SKumar Gala * TTL = duty cycle 4999490a7f1SKumar Gala * C1:C0 = internal load capacitance for cyrstal 5009490a7f1SKumar Gala */ 5019490a7f1SKumar Gala 5029490a7f1SKumar Gala /* Adding 1 to get a "nicely" rounded number, but this needs 5039490a7f1SKumar Gala * more tweaking to get a "properly" rounded number. */ 5049490a7f1SKumar Gala 5059490a7f1SKumar Gala freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 5069490a7f1SKumar Gala 5079490a7f1SKumar Gala debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 5089490a7f1SKumar Gala freq); 5099490a7f1SKumar Gala return freq; 5109490a7f1SKumar Gala } 5119490a7f1SKumar Gala 5129490a7f1SKumar Gala unsigned long 5139490a7f1SKumar Gala get_board_sys_clk(ulong dummy) 5149490a7f1SKumar Gala { 5159490a7f1SKumar Gala return ics307_clk_freq ( 5169490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_VSYSCLK0), 5179490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_VSYSCLK1), 5189490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_VSYSCLK2) 5199490a7f1SKumar Gala ); 5209490a7f1SKumar Gala } 5219490a7f1SKumar Gala 5229490a7f1SKumar Gala unsigned long 5239490a7f1SKumar Gala get_board_ddr_clk(ulong dummy) 5249490a7f1SKumar Gala { 5259490a7f1SKumar Gala return ics307_clk_freq ( 5269490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_VDDRCLK0), 5279490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_VDDRCLK1), 5289490a7f1SKumar Gala in8(PIXIS_BASE + PIXIS_VDDRCLK2) 5299490a7f1SKumar Gala ); 5309490a7f1SKumar Gala } 5319490a7f1SKumar Gala #else 5329490a7f1SKumar Gala unsigned long 5339490a7f1SKumar Gala get_board_sys_clk(ulong dummy) 5349490a7f1SKumar Gala { 5359490a7f1SKumar Gala u8 i; 5369490a7f1SKumar Gala ulong val = 0; 5379490a7f1SKumar Gala 5389490a7f1SKumar Gala i = in8(PIXIS_BASE + PIXIS_SPD); 5399490a7f1SKumar Gala i &= 0x07; 5409490a7f1SKumar Gala 5419490a7f1SKumar Gala switch (i) { 5429490a7f1SKumar Gala case 0: 5439490a7f1SKumar Gala val = 33333333; 5449490a7f1SKumar Gala break; 5459490a7f1SKumar Gala case 1: 5469490a7f1SKumar Gala val = 40000000; 5479490a7f1SKumar Gala break; 5489490a7f1SKumar Gala case 2: 5499490a7f1SKumar Gala val = 50000000; 5509490a7f1SKumar Gala break; 5519490a7f1SKumar Gala case 3: 5529490a7f1SKumar Gala val = 66666666; 5539490a7f1SKumar Gala break; 5549490a7f1SKumar Gala case 4: 5559490a7f1SKumar Gala val = 83333333; 5569490a7f1SKumar Gala break; 5579490a7f1SKumar Gala case 5: 5589490a7f1SKumar Gala val = 100000000; 5599490a7f1SKumar Gala break; 5609490a7f1SKumar Gala case 6: 5619490a7f1SKumar Gala val = 133333333; 5629490a7f1SKumar Gala break; 5639490a7f1SKumar Gala case 7: 5649490a7f1SKumar Gala val = 166666666; 5659490a7f1SKumar Gala break; 5669490a7f1SKumar Gala } 5679490a7f1SKumar Gala 5689490a7f1SKumar Gala return val; 5699490a7f1SKumar Gala } 5709490a7f1SKumar Gala 5719490a7f1SKumar Gala unsigned long 5729490a7f1SKumar Gala get_board_ddr_clk(ulong dummy) 5739490a7f1SKumar Gala { 5749490a7f1SKumar Gala u8 i; 5759490a7f1SKumar Gala ulong val = 0; 5769490a7f1SKumar Gala 5779490a7f1SKumar Gala i = in8(PIXIS_BASE + PIXIS_SPD); 5789490a7f1SKumar Gala i &= 0x38; 5799490a7f1SKumar Gala i >>= 3; 5809490a7f1SKumar Gala 5819490a7f1SKumar Gala switch (i) { 5829490a7f1SKumar Gala case 0: 5839490a7f1SKumar Gala val = 33333333; 5849490a7f1SKumar Gala break; 5859490a7f1SKumar Gala case 1: 5869490a7f1SKumar Gala val = 40000000; 5879490a7f1SKumar Gala break; 5889490a7f1SKumar Gala case 2: 5899490a7f1SKumar Gala val = 50000000; 5909490a7f1SKumar Gala break; 5919490a7f1SKumar Gala case 3: 5929490a7f1SKumar Gala val = 66666666; 5939490a7f1SKumar Gala break; 5949490a7f1SKumar Gala case 4: 5959490a7f1SKumar Gala val = 83333333; 5969490a7f1SKumar Gala break; 5979490a7f1SKumar Gala case 5: 5989490a7f1SKumar Gala val = 100000000; 5999490a7f1SKumar Gala break; 6009490a7f1SKumar Gala case 6: 6019490a7f1SKumar Gala val = 133333333; 6029490a7f1SKumar Gala break; 6039490a7f1SKumar Gala case 7: 6049490a7f1SKumar Gala val = 166666666; 6059490a7f1SKumar Gala break; 6069490a7f1SKumar Gala } 6079490a7f1SKumar Gala return val; 6089490a7f1SKumar Gala } 6099490a7f1SKumar Gala #endif 6109490a7f1SKumar Gala 611*0f8cbc18SJason Jin int is_sata_supported() 612*0f8cbc18SJason Jin { 613*0f8cbc18SJason Jin volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 614*0f8cbc18SJason Jin uint devdisr = gur->devdisr; 615*0f8cbc18SJason Jin uint sdrs2_io_sel = 616*0f8cbc18SJason Jin (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 617*0f8cbc18SJason Jin if (sdrs2_io_sel & 0x04) 618*0f8cbc18SJason Jin return 0; 619*0f8cbc18SJason Jin 620*0f8cbc18SJason Jin return 1; 621*0f8cbc18SJason Jin } 622*0f8cbc18SJason Jin 6239490a7f1SKumar Gala #if defined(CONFIG_OF_BOARD_SETUP) 6249490a7f1SKumar Gala void 6259490a7f1SKumar Gala ft_board_setup(void *blob, bd_t *bd) 6269490a7f1SKumar Gala { 6279490a7f1SKumar Gala int node, tmp[2]; 6289490a7f1SKumar Gala const char *path; 6299490a7f1SKumar Gala 6309490a7f1SKumar Gala ft_cpu_setup(blob, bd); 6319490a7f1SKumar Gala 6329490a7f1SKumar Gala node = fdt_path_offset(blob, "/aliases"); 6339490a7f1SKumar Gala tmp[0] = 0; 6349490a7f1SKumar Gala if (node >= 0) { 6359490a7f1SKumar Gala #ifdef CONFIG_PCI1 6369490a7f1SKumar Gala path = fdt_getprop(blob, node, "pci0", NULL); 6379490a7f1SKumar Gala if (path) { 6389490a7f1SKumar Gala tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 6399490a7f1SKumar Gala do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 6409490a7f1SKumar Gala } 6419490a7f1SKumar Gala #endif 6429490a7f1SKumar Gala #ifdef CONFIG_PCIE2 6439490a7f1SKumar Gala path = fdt_getprop(blob, node, "pci1", NULL); 6449490a7f1SKumar Gala if (path) { 6459490a7f1SKumar Gala tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; 6469490a7f1SKumar Gala do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 6479490a7f1SKumar Gala } 6489490a7f1SKumar Gala #endif 6499490a7f1SKumar Gala #ifdef CONFIG_PCIE1 6509490a7f1SKumar Gala path = fdt_getprop(blob, node, "pci2", NULL); 6519490a7f1SKumar Gala if (path) { 6529490a7f1SKumar Gala tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 6539490a7f1SKumar Gala do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 6549490a7f1SKumar Gala } 6559490a7f1SKumar Gala #endif 6569490a7f1SKumar Gala #ifdef CONFIG_PCIE3 6579490a7f1SKumar Gala path = fdt_getprop(blob, node, "pci3", NULL); 6589490a7f1SKumar Gala if (path) { 6599490a7f1SKumar Gala tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; 6609490a7f1SKumar Gala do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 6619490a7f1SKumar Gala } 6629490a7f1SKumar Gala #endif 6639490a7f1SKumar Gala } 6649490a7f1SKumar Gala } 6659490a7f1SKumar Gala #endif 666