1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0 29490a7f1SKumar Gala /* 39490a7f1SKumar Gala * Copyright 2008 Freescale Semiconductor, Inc. 49490a7f1SKumar Gala */ 59490a7f1SKumar Gala 69490a7f1SKumar Gala #include <common.h> 79490a7f1SKumar Gala 85614e71bSYork Sun #include <fsl_ddr_sdram.h> 95614e71bSYork Sun #include <fsl_ddr_dimm_params.h> 109490a7f1SKumar Gala 11dfb49108SHaiying Wang void fsl_ddr_board_options(memctl_options_t *popts, 12dfb49108SHaiying Wang dimm_params_t *pdimm, 13dfb49108SHaiying Wang unsigned int ctrl_num) 149490a7f1SKumar Gala { 159490a7f1SKumar Gala /* 169490a7f1SKumar Gala * Factors to consider for clock adjust: 179490a7f1SKumar Gala * - number of chips on bus 189490a7f1SKumar Gala * - position of slot 199490a7f1SKumar Gala * - DDR1 vs. DDR2? 209490a7f1SKumar Gala * - ??? 219490a7f1SKumar Gala * 229490a7f1SKumar Gala * This needs to be determined on a board-by-board basis. 239490a7f1SKumar Gala * 0110 3/4 cycle late 249490a7f1SKumar Gala * 0111 7/8 cycle late 259490a7f1SKumar Gala */ 269490a7f1SKumar Gala popts->clk_adjust = 7; 279490a7f1SKumar Gala 289490a7f1SKumar Gala /* 299490a7f1SKumar Gala * Factors to consider for CPO: 309490a7f1SKumar Gala * - frequency 319490a7f1SKumar Gala * - ddr1 vs. ddr2 329490a7f1SKumar Gala */ 339490a7f1SKumar Gala popts->cpo_override = 10; 349490a7f1SKumar Gala 359490a7f1SKumar Gala /* 369490a7f1SKumar Gala * Factors to consider for write data delay: 379490a7f1SKumar Gala * - number of DIMMs 389490a7f1SKumar Gala * 399490a7f1SKumar Gala * 1 = 1/4 clock delay 409490a7f1SKumar Gala * 2 = 1/2 clock delay 419490a7f1SKumar Gala * 3 = 3/4 clock delay 429490a7f1SKumar Gala * 4 = 1 clock delay 439490a7f1SKumar Gala * 5 = 5/4 clock delay 449490a7f1SKumar Gala * 6 = 3/2 clock delay 459490a7f1SKumar Gala */ 469490a7f1SKumar Gala popts->write_data_delay = 3; 479490a7f1SKumar Gala 489490a7f1SKumar Gala /* 499490a7f1SKumar Gala * Factors to consider for half-strength driver enable: 509490a7f1SKumar Gala * - number of DIMMs installed 519490a7f1SKumar Gala */ 529490a7f1SKumar Gala popts->half_strength_driver_enable = 0; 53bf5b1f0cSDave Liu 54bf5b1f0cSDave Liu /* 55bf5b1f0cSDave Liu * For wake up arp feature, we need enable auto self refresh 56bf5b1f0cSDave Liu */ 57bf5b1f0cSDave Liu popts->auto_self_refresh_en = 1; 58bf5b1f0cSDave Liu popts->sr_it = 0x6; 599490a7f1SKumar Gala } 60