1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Kevin Lam <kevin.lam@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <hwconfig.h> 11 #include <i2c.h> 12 #include <asm/io.h> 13 #include <asm/fsl_mpc83xx_serdes.h> 14 #include <fdt_support.h> 15 #include <spd_sdram.h> 16 #include <vsc7385.h> 17 #include <fsl_esdhc.h> 18 19 #if defined(CONFIG_SYS_DRAM_TEST) 20 int 21 testdram(void) 22 { 23 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 24 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 25 uint *p; 26 27 printf("Testing DRAM from 0x%08x to 0x%08x\n", 28 CONFIG_SYS_MEMTEST_START, 29 CONFIG_SYS_MEMTEST_END); 30 31 printf("DRAM test phase 1:\n"); 32 for (p = pstart; p < pend; p++) 33 *p = 0xaaaaaaaa; 34 35 for (p = pstart; p < pend; p++) { 36 if (*p != 0xaaaaaaaa) { 37 printf("DRAM test fails at: %08x\n", (uint) p); 38 return 1; 39 } 40 } 41 42 printf("DRAM test phase 2:\n"); 43 for (p = pstart; p < pend; p++) 44 *p = 0x55555555; 45 46 for (p = pstart; p < pend; p++) { 47 if (*p != 0x55555555) { 48 printf("DRAM test fails at: %08x\n", (uint) p); 49 return 1; 50 } 51 } 52 53 printf("DRAM test passed.\n"); 54 return 0; 55 } 56 #endif 57 58 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 59 void ddr_enable_ecc(unsigned int dram_size); 60 #endif 61 int fixed_sdram(void); 62 63 phys_size_t initdram(int board_type) 64 { 65 immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 66 u32 msize = 0; 67 68 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 69 return -1; 70 71 #if defined(CONFIG_SPD_EEPROM) 72 msize = spd_sdram(); 73 #else 74 msize = fixed_sdram(); 75 #endif 76 77 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 78 /* Initialize DDR ECC byte */ 79 ddr_enable_ecc(msize * 1024 * 1024); 80 #endif 81 /* return total bus DDR size(bytes) */ 82 return (msize * 1024 * 1024); 83 } 84 85 #if !defined(CONFIG_SPD_EEPROM) 86 /************************************************************************* 87 * fixed sdram init -- doesn't use serial presence detect. 88 ************************************************************************/ 89 int fixed_sdram(void) 90 { 91 immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 92 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; 93 u32 msize_log2 = __ilog2(msize); 94 95 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 96 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); 97 98 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; 99 udelay(50000); 100 101 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; 102 udelay(1000); 103 104 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; 105 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; 106 udelay(1000); 107 108 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 109 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 110 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 111 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 112 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; 113 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; 114 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 115 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; 116 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 117 sync(); 118 udelay(1000); 119 120 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 121 udelay(2000); 122 return CONFIG_SYS_DDR_SIZE; 123 } 124 #endif /*!CONFIG_SYS_SPD_EEPROM */ 125 126 int checkboard(void) 127 { 128 puts("Board: Freescale MPC837xERDB\n"); 129 return 0; 130 } 131 132 int board_early_init_f(void) 133 { 134 #ifdef CONFIG_FSL_SERDES 135 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 136 u32 spridr = in_be32(&immr->sysconf.spridr); 137 138 /* we check only part num, and don't look for CPU revisions */ 139 switch (PARTID_NO_E(spridr)) { 140 case SPR_8377: 141 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, 142 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 143 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, 144 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 145 break; 146 case SPR_8378: 147 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, 148 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 149 break; 150 case SPR_8379: 151 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, 152 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 153 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, 154 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 155 break; 156 default: 157 printf("serdes not configured: unknown CPU part number: " 158 "%04x\n", spridr >> 16); 159 break; 160 } 161 #endif /* CONFIG_FSL_SERDES */ 162 return 0; 163 } 164 165 #ifdef CONFIG_FSL_ESDHC 166 int board_mmc_init(bd_t *bd) 167 { 168 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; 169 170 if (!hwconfig("esdhc")) 171 return 0; 172 173 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); 174 clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD); 175 176 return fsl_esdhc_mmc_init(bd); 177 } 178 #endif 179 180 /* 181 * Miscellaneous late-boot configurations 182 * 183 * If a VSC7385 microcode image is present, then upload it. 184 */ 185 int misc_init_r(void) 186 { 187 int rc = 0; 188 189 #ifdef CONFIG_VSC7385_IMAGE 190 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, 191 CONFIG_VSC7385_IMAGE_SIZE)) { 192 puts("Failure uploading VSC7385 microcode.\n"); 193 rc = 1; 194 } 195 #endif 196 197 return rc; 198 } 199 200 #if defined(CONFIG_OF_BOARD_SETUP) 201 202 void ft_board_setup(void *blob, bd_t *bd) 203 { 204 #ifdef CONFIG_PCI 205 ft_pci_setup(blob, bd); 206 #endif 207 ft_cpu_setup(blob, bd); 208 fdt_fixup_dr_usb(blob, bd); 209 fdt_fixup_esdhc(blob, bd); 210 } 211 #endif /* CONFIG_OF_BOARD_SETUP */ 212