1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Kevin Lam <kevin.lam@freescale.com>
4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  */
14 
15 #include <common.h>
16 #include <i2c.h>
17 #include <spd.h>
18 #include <asm/io.h>
19 #if defined(CONFIG_SPD_EEPROM)
20 #include <spd_sdram.h>
21 #endif
22 
23 #if defined(CFG_DRAM_TEST)
24 int
25 testdram(void)
26 {
27 	uint *pstart = (uint *) CFG_MEMTEST_START;
28 	uint *pend = (uint *) CFG_MEMTEST_END;
29 	uint *p;
30 
31 	printf("Testing DRAM from 0x%08x to 0x%08x\n",
32 	       CFG_MEMTEST_START,
33 	       CFG_MEMTEST_END);
34 
35 	printf("DRAM test phase 1:\n");
36 	for (p = pstart; p < pend; p++)
37 		*p = 0xaaaaaaaa;
38 
39 	for (p = pstart; p < pend; p++) {
40 		if (*p != 0xaaaaaaaa) {
41 			printf("DRAM test fails at: %08x\n", (uint) p);
42 			return 1;
43 		}
44 	}
45 
46 	printf("DRAM test phase 2:\n");
47 	for (p = pstart; p < pend; p++)
48 		*p = 0x55555555;
49 
50 	for (p = pstart; p < pend; p++) {
51 		if (*p != 0x55555555) {
52 			printf("DRAM test fails at: %08x\n", (uint) p);
53 			return 1;
54 		}
55 	}
56 
57 	printf("DRAM test passed.\n");
58 	return 0;
59 }
60 #endif
61 
62 int board_early_init_f(void)
63 {
64 	return 0;
65 }
66 
67 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
68 void ddr_enable_ecc(unsigned int dram_size);
69 #endif
70 int fixed_sdram(void);
71 
72 long int initdram(int board_type)
73 {
74 	immap_t *im = (immap_t *) CFG_IMMR;
75 	u32 msize = 0;
76 
77 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
78 		return -1;
79 
80 #if defined(CONFIG_SPD_EEPROM)
81 	msize = spd_sdram();
82 #else
83 	msize = fixed_sdram();
84 #endif
85 
86 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
87 	/* Initialize DDR ECC byte */
88 	ddr_enable_ecc(msize * 1024 * 1024);
89 #endif
90 	/* return total bus DDR size(bytes) */
91 	return (msize * 1024 * 1024);
92 }
93 
94 #if !defined(CONFIG_SPD_EEPROM)
95 /*************************************************************************
96  *  fixed sdram init -- doesn't use serial presence detect.
97  ************************************************************************/
98 int fixed_sdram(void)
99 {
100 	immap_t *im = (immap_t *) CFG_IMMR;
101 	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
102 	u32 msize_log2 = __ilog2(msize);
103 
104 	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
105 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
106 
107 	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
108 	udelay(50000);
109 
110 	im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
111 	udelay(1000);
112 
113 	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
114 	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
115 	udelay(1000);
116 
117 	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
118 	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
119 	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
120 	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
121 	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
122 	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
123 	im->ddr.sdram_mode = CFG_DDR_MODE;
124 	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
125 	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
126 	sync();
127 	udelay(1000);
128 
129 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
130 	udelay(2000);
131 	return CFG_DDR_SIZE;
132 }
133 #endif	/*!CFG_SPD_EEPROM */
134 
135 int checkboard(void)
136 {
137 	puts("Board: Freescale MPC837xERDB\n");
138 	return 0;
139 }
140 
141 #if defined(CONFIG_OF_BOARD_SETUP)
142 
143 void ft_board_setup(void *blob, bd_t *bd)
144 {
145 #ifdef CONFIG_PCI
146 	ft_pci_setup(blob, bd);
147 #endif
148 	ft_cpu_setup(blob, bd);
149 }
150 #endif /* CONFIG_OF_BOARD_SETUP */
151