1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2007 Freescale Semiconductor, Inc. 4 * Kevin Lam <kevin.lam@freescale.com> 5 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 6 */ 7 8 #include <common.h> 9 #include <hwconfig.h> 10 #include <i2c.h> 11 #include <asm/io.h> 12 #include <asm/fsl_mpc83xx_serdes.h> 13 #include <fdt_support.h> 14 #include <spd_sdram.h> 15 #include <vsc7385.h> 16 #include <fsl_esdhc.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #if defined(CONFIG_SYS_DRAM_TEST) 21 int 22 testdram(void) 23 { 24 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 25 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 26 uint *p; 27 28 printf("Testing DRAM from 0x%08x to 0x%08x\n", 29 CONFIG_SYS_MEMTEST_START, 30 CONFIG_SYS_MEMTEST_END); 31 32 printf("DRAM test phase 1:\n"); 33 for (p = pstart; p < pend; p++) 34 *p = 0xaaaaaaaa; 35 36 for (p = pstart; p < pend; p++) { 37 if (*p != 0xaaaaaaaa) { 38 printf("DRAM test fails at: %08x\n", (uint) p); 39 return 1; 40 } 41 } 42 43 printf("DRAM test phase 2:\n"); 44 for (p = pstart; p < pend; p++) 45 *p = 0x55555555; 46 47 for (p = pstart; p < pend; p++) { 48 if (*p != 0x55555555) { 49 printf("DRAM test fails at: %08x\n", (uint) p); 50 return 1; 51 } 52 } 53 54 printf("DRAM test passed.\n"); 55 return 0; 56 } 57 #endif 58 59 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 60 void ddr_enable_ecc(unsigned int dram_size); 61 #endif 62 int fixed_sdram(void); 63 64 int dram_init(void) 65 { 66 immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 67 u32 msize = 0; 68 69 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 70 return -ENXIO; 71 72 #if defined(CONFIG_SPD_EEPROM) 73 msize = spd_sdram(); 74 #else 75 msize = fixed_sdram(); 76 #endif 77 78 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 79 /* Initialize DDR ECC byte */ 80 ddr_enable_ecc(msize * 1024 * 1024); 81 #endif 82 /* return total bus DDR size(bytes) */ 83 gd->ram_size = msize * 1024 * 1024; 84 85 return 0; 86 } 87 88 #if !defined(CONFIG_SPD_EEPROM) 89 /************************************************************************* 90 * fixed sdram init -- doesn't use serial presence detect. 91 ************************************************************************/ 92 int fixed_sdram(void) 93 { 94 immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 95 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; 96 u32 msize_log2 = __ilog2(msize); 97 98 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 99 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); 100 101 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; 102 udelay(50000); 103 104 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; 105 udelay(1000); 106 107 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; 108 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; 109 udelay(1000); 110 111 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 112 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 113 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 114 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 115 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; 116 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; 117 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 118 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; 119 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 120 sync(); 121 udelay(1000); 122 123 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 124 udelay(2000); 125 return CONFIG_SYS_DDR_SIZE; 126 } 127 #endif /*!CONFIG_SYS_SPD_EEPROM */ 128 129 int checkboard(void) 130 { 131 puts("Board: Freescale MPC837xERDB\n"); 132 return 0; 133 } 134 135 int board_early_init_f(void) 136 { 137 #ifdef CONFIG_FSL_SERDES 138 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 139 u32 spridr = in_be32(&immr->sysconf.spridr); 140 141 /* we check only part num, and don't look for CPU revisions */ 142 switch (PARTID_NO_E(spridr)) { 143 case SPR_8377: 144 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, 145 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 146 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, 147 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 148 break; 149 case SPR_8378: 150 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, 151 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 152 break; 153 case SPR_8379: 154 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, 155 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 156 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, 157 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 158 break; 159 default: 160 printf("serdes not configured: unknown CPU part number: " 161 "%04x\n", spridr >> 16); 162 break; 163 } 164 #endif /* CONFIG_FSL_SERDES */ 165 return 0; 166 } 167 168 #ifdef CONFIG_FSL_ESDHC 169 int board_mmc_init(bd_t *bd) 170 { 171 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; 172 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 173 int esdhc_hwconfig_enabled = 0; 174 175 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) 176 esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer); 177 178 if (esdhc_hwconfig_enabled == 0) 179 return 0; 180 181 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); 182 clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD); 183 184 return fsl_esdhc_mmc_init(bd); 185 } 186 #endif 187 188 /* 189 * Miscellaneous late-boot configurations 190 * 191 * If a VSC7385 microcode image is present, then upload it. 192 */ 193 int misc_init_r(void) 194 { 195 int rc = 0; 196 197 #ifdef CONFIG_VSC7385_IMAGE 198 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, 199 CONFIG_VSC7385_IMAGE_SIZE)) { 200 puts("Failure uploading VSC7385 microcode.\n"); 201 rc = 1; 202 } 203 #endif 204 205 return rc; 206 } 207 208 #if defined(CONFIG_OF_BOARD_SETUP) 209 210 int ft_board_setup(void *blob, bd_t *bd) 211 { 212 #ifdef CONFIG_PCI 213 ft_pci_setup(blob, bd); 214 #endif 215 ft_cpu_setup(blob, bd); 216 fsl_fdt_fixup_dr_usb(blob, bd); 217 fdt_fixup_esdhc(blob, bd); 218 219 return 0; 220 } 221 #endif /* CONFIG_OF_BOARD_SETUP */ 222