1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * CREDITS: Kim Phillips contribute to LIBFDT code 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 #include <common.h> 14 #include <i2c.h> 15 #include <asm/io.h> 16 #include <asm/fsl_serdes.h> 17 #include <spd_sdram.h> 18 #if defined(CONFIG_OF_LIBFDT) 19 #include <libfdt.h> 20 #endif 21 #if defined(CONFIG_PQ_MDS_PIB) 22 #include "../common/pq-mds-pib.h" 23 #endif 24 25 int board_early_init_f(void) 26 { 27 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; 28 29 /* Enable flash write */ 30 bcsr[0x9] &= ~0x04; 31 /* Clear all of the interrupt of BCSR */ 32 bcsr[0xe] = 0xff; 33 34 #ifdef CONFIG_FSL_SERDES 35 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 36 u32 spridr = in_be32(&immr->sysconf.spridr); 37 38 /* we check only part num, and don't look for CPU revisions */ 39 switch (PARTID_NO_E(spridr)) { 40 case SPR_8377: 41 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, 42 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 43 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, 44 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 45 break; 46 case SPR_8378: 47 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, 48 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 49 break; 50 case SPR_8379: 51 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, 52 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 53 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, 54 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 55 break; 56 default: 57 printf("serdes not configured: unknown CPU part number: " 58 "%04x\n", spridr >> 16); 59 break; 60 } 61 #endif /* CONFIG_FSL_SERDES */ 62 return 0; 63 } 64 65 int board_early_init_r(void) 66 { 67 #ifdef CONFIG_PQ_MDS_PIB 68 pib_init(); 69 #endif 70 return 0; 71 } 72 73 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 74 extern void ddr_enable_ecc(unsigned int dram_size); 75 #endif 76 int fixed_sdram(void); 77 78 phys_size_t initdram(int board_type) 79 { 80 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 81 u32 msize = 0; 82 83 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 84 return -1; 85 86 #if defined(CONFIG_SPD_EEPROM) 87 msize = spd_sdram(); 88 #else 89 msize = fixed_sdram(); 90 #endif 91 92 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 93 /* Initialize DDR ECC byte */ 94 ddr_enable_ecc(msize * 1024 * 1024); 95 #endif 96 97 /* return total bus DDR size(bytes) */ 98 return (msize * 1024 * 1024); 99 } 100 101 #if !defined(CONFIG_SPD_EEPROM) 102 /************************************************************************* 103 * fixed sdram init -- doesn't use serial presence detect. 104 ************************************************************************/ 105 int fixed_sdram(void) 106 { 107 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 108 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; 109 u32 msize_log2 = __ilog2(msize); 110 111 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 112 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); 113 114 #if (CONFIG_SYS_DDR_SIZE != 512) 115 #warning Currenly any ddr size other than 512 is not supported 116 #endif 117 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; 118 udelay(50000); 119 120 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; 121 udelay(1000); 122 123 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; 124 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; 125 udelay(1000); 126 127 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 128 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 129 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 130 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 131 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; 132 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; 133 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 134 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; 135 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 136 __asm__ __volatile__("sync"); 137 udelay(1000); 138 139 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 140 udelay(2000); 141 return CONFIG_SYS_DDR_SIZE; 142 } 143 #endif /*!CONFIG_SYS_SPD_EEPROM */ 144 145 int checkboard(void) 146 { 147 puts("Board: Freescale MPC837xEMDS\n"); 148 return 0; 149 } 150 151 #if defined(CONFIG_OF_BOARD_SETUP) 152 void ft_board_setup(void *blob, bd_t *bd) 153 { 154 ft_cpu_setup(blob, bd); 155 #ifdef CONFIG_PCI 156 ft_pci_setup(blob, bd); 157 #endif 158 } 159 #endif /* CONFIG_OF_BOARD_SETUP */ 160