1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Dave Liu <daveliu@freescale.com>
4  *
5  * CREDITS: Kim Phillips contribute to LIBFDT code
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  */
12 
13 #include <common.h>
14 #include <i2c.h>
15 #include <spd.h>
16 #if defined(CONFIG_SPD_EEPROM)
17 #include <spd_sdram.h>
18 #endif
19 #if defined(CONFIG_OF_LIBFDT)
20 #include <libfdt.h>
21 #endif
22 #if defined(CONFIG_PQ_MDS_PIB)
23 #include "../common/pq-mds-pib.h"
24 #endif
25 
26 int board_early_init_f(void)
27 {
28 	u8 *bcsr = (u8 *)CFG_BCSR;
29 
30 	/* Enable flash write */
31 	bcsr[0x9] &= ~0x04;
32 	/* Clear all of the interrupt of BCSR */
33 	bcsr[0xe] = 0xff;
34 
35 	return 0;
36 }
37 
38 int board_early_init_r(void)
39 {
40 #ifdef CONFIG_PQ_MDS_PIB
41 	pib_init();
42 #endif
43 	return 0;
44 }
45 
46 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
47 extern void ddr_enable_ecc(unsigned int dram_size);
48 #endif
49 int fixed_sdram(void);
50 
51 long int initdram(int board_type)
52 {
53 	volatile immap_t *im = (immap_t *) CFG_IMMR;
54 	u32 msize = 0;
55 
56 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
57 		return -1;
58 
59 #if defined(CONFIG_SPD_EEPROM)
60 	msize = spd_sdram();
61 #else
62 	msize = fixed_sdram();
63 #endif
64 
65 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
66 	/* Initialize DDR ECC byte */
67 	ddr_enable_ecc(msize * 1024 * 1024);
68 #endif
69 
70 	/* return total bus DDR size(bytes) */
71 	return (msize * 1024 * 1024);
72 }
73 
74 #if !defined(CONFIG_SPD_EEPROM)
75 /*************************************************************************
76  *  fixed sdram init -- doesn't use serial presence detect.
77  ************************************************************************/
78 int fixed_sdram(void)
79 {
80 	volatile immap_t *im = (immap_t *) CFG_IMMR;
81 	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
82 	u32 msize_log2 = __ilog2(msize);
83 
84 	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
85 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
86 
87 #if (CFG_DDR_SIZE != 512)
88 #warning Currenly any ddr size other than 512 is not supported
89 #endif
90 	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
91 	udelay(50000);
92 
93 	im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
94 	udelay(1000);
95 
96 	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
97 	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
98 	udelay(1000);
99 
100 	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
101 	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
102 	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
103 	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
104 	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
105 	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
106 	im->ddr.sdram_mode = CFG_DDR_MODE;
107 	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
108 	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
109 	__asm__ __volatile__("sync");
110 	udelay(1000);
111 
112 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
113 	udelay(2000);
114 	return CFG_DDR_SIZE;
115 }
116 #endif /*!CFG_SPD_EEPROM */
117 
118 int checkboard(void)
119 {
120 	puts("Board: Freescale MPC837xEMDS\n");
121 	return 0;
122 }
123 
124 #if defined(CONFIG_OF_BOARD_SETUP)
125 void ft_board_setup(void *blob, bd_t *bd)
126 {
127 	ft_cpu_setup(blob, bd);
128 #ifdef CONFIG_PCI
129 	ft_pci_setup(blob, bd);
130 #endif
131 }
132 #endif /* CONFIG_OF_BOARD_SETUP */
133