1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <ioports.h> 9 #include <mpc83xx.h> 10 #include <i2c.h> 11 #include <miiphy.h> 12 #include <vsc7385.h> 13 #ifdef CONFIG_PCI 14 #include <asm/mpc8349_pci.h> 15 #include <pci.h> 16 #endif 17 #include <spd_sdram.h> 18 #include <asm/mmu.h> 19 #if defined(CONFIG_OF_LIBFDT) 20 #include <libfdt.h> 21 #endif 22 23 #ifndef CONFIG_SPD_EEPROM 24 /************************************************************************* 25 * fixed sdram init -- doesn't use serial presence detect. 26 ************************************************************************/ 27 int fixed_sdram(void) 28 { 29 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 30 /* The size of RAM, in bytes */ 31 u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20; 32 u32 ddr_size_log2 = __ilog2(ddr_size); 33 34 im->sysconf.ddrlaw[0].ar = 35 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 36 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 37 38 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) 39 #warning Chip select bounds is only configurable in 16MB increments 40 #endif 41 im->ddr.csbnds[0].csbnds = 42 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | 43 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> 44 CSBNDS_EA_SHIFT) & CSBNDS_EA); 45 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; 46 47 /* Only one CS for DDR */ 48 im->ddr.cs_config[1] = 0; 49 im->ddr.cs_config[2] = 0; 50 im->ddr.cs_config[3] = 0; 51 52 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); 53 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); 54 55 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); 56 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); 57 58 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 59 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ 60 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; 61 im->ddr.sdram_mode = 62 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); 63 im->ddr.sdram_interval = 64 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << 65 SDRAM_INTERVAL_BSTOPRE_SHIFT); 66 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; 67 68 udelay(200); 69 70 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 71 72 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); 73 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); 74 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); 75 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); 76 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); 77 78 return CONFIG_SYS_DDR_SIZE; 79 } 80 #endif 81 82 #ifdef CONFIG_PCI 83 /* 84 * Initialize PCI Devices, report devices found 85 */ 86 #ifndef CONFIG_PCI_PNP 87 static struct pci_config_table pci_mpc83xxmitx_config_table[] = { 88 { 89 PCI_ANY_ID, 90 PCI_ANY_ID, 91 PCI_ANY_ID, 92 PCI_ANY_ID, 93 0x0f, 94 PCI_ANY_ID, 95 pci_cfgfunc_config_device, 96 { 97 PCI_ENET0_IOADDR, 98 PCI_ENET0_MEMADDR, 99 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} 100 }, 101 {} 102 } 103 #endif 104 105 volatile static struct pci_controller hose[] = { 106 { 107 #ifndef CONFIG_PCI_PNP 108 config_table:pci_mpc83xxmitx_config_table, 109 #endif 110 }, 111 { 112 #ifndef CONFIG_PCI_PNP 113 config_table:pci_mpc83xxmitx_config_table, 114 #endif 115 } 116 }; 117 #endif /* CONFIG_PCI */ 118 119 phys_size_t initdram(int board_type) 120 { 121 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 122 u32 msize = 0; 123 #ifdef CONFIG_DDR_ECC 124 volatile ddr83xx_t *ddr = &im->ddr; 125 #endif 126 127 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 128 return -1; 129 130 /* DDR SDRAM - Main SODIMM */ 131 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 132 #ifdef CONFIG_SPD_EEPROM 133 msize = spd_sdram(); 134 #else 135 msize = fixed_sdram(); 136 #endif 137 138 #ifdef CONFIG_DDR_ECC 139 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) 140 /* Unlike every other board, on the 83xx spd_sdram() returns 141 megabytes instead of just bytes. That's why we need to 142 multiple by 1MB when calling ddr_enable_ecc(). */ 143 ddr_enable_ecc(msize * 1048576); 144 #endif 145 146 /* return total bus RAM size(bytes) */ 147 return msize * 1024 * 1024; 148 } 149 150 int checkboard(void) 151 { 152 #ifdef CONFIG_MPC8349ITX 153 puts("Board: Freescale MPC8349E-mITX\n"); 154 #else 155 puts("Board: Freescale MPC8349E-mITX-GP\n"); 156 #endif 157 158 return 0; 159 } 160 161 /* 162 * Implement a work-around for a hardware problem with compact 163 * flash. 164 * 165 * Program the UPM if compact flash is enabled. 166 */ 167 int misc_init_f(void) 168 { 169 #ifdef CONFIG_VSC7385_ENET 170 volatile u32 *vsc7385_cpuctrl; 171 172 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up 173 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That 174 means it is 0 when the IRQ is not active. This makes the wire-AND 175 logic always assert IRQ7 to CPU even if there is no request from the 176 switch. Since the compact flash and the switch share the same IRQ, 177 the Linux kernel will think that the compact flash is requesting irq 178 and get stuck when it tries to clear the IRQ. Thus we need to set 179 the L2_IRQ0 and L2_IRQ1 to active low. 180 181 The following code sets the L1_IRQ and L2_IRQ polarity to active low. 182 Without this code, compact flash will not work in Linux because 183 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we 184 don't enable compact flash for U-Boot. 185 */ 186 187 vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0); 188 *vsc7385_cpuctrl |= 0x0c; 189 #endif 190 191 #ifdef CONFIG_COMPACT_FLASH 192 /* UPM Table Configuration Code */ 193 static uint UPMATable[] = { 194 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, 195 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, 196 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 197 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 198 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, 199 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 200 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, 201 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, 202 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 203 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 204 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 205 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 206 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 207 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 208 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 209 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 210 }; 211 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 212 213 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); 214 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); 215 216 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, 217 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 218 */ 219 immap->im_lbc.mamr = 0x08404440; 220 221 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); 222 223 puts("UPMA: Configured for compact flash\n"); 224 #endif 225 226 return 0; 227 } 228 229 /* 230 * Miscellaneous late-boot configurations 231 * 232 * Make sure the EEPROM has the HRCW correctly programmed. 233 * Make sure the RTC is correctly programmed. 234 * 235 * The MPC8349E-mITX can be configured to load the HRCW from 236 * EEPROM instead of flash. This is controlled via jumpers 237 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all 238 * jumpered), but if they're set to 001 or 010, then the HRCW is 239 * read from the "I2C EEPROM". 240 * 241 * This function makes sure that the I2C EEPROM is programmed 242 * correctly. 243 * 244 * If a VSC7385 microcode image is present, then upload it. 245 */ 246 int misc_init_r(void) 247 { 248 int rc = 0; 249 250 #if defined(CONFIG_SYS_I2C) 251 unsigned int orig_bus = i2c_get_bus_num(); 252 u8 i2c_data; 253 254 #ifdef CONFIG_SYS_I2C_RTC_ADDR 255 u8 ds1339_data[17]; 256 #endif 257 258 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR 259 static u8 eeprom_data[] = /* HRCW data */ 260 { 261 0xAA, 0x55, 0xAA, /* Preamble */ 262 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ 263 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ 264 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF, 265 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF, 266 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF, 267 CONFIG_SYS_HRCW_LOW & 0xFF, 268 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ 269 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ 270 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF, 271 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF, 272 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF, 273 CONFIG_SYS_HRCW_HIGH & 0xFF 274 }; 275 276 u8 data[sizeof(eeprom_data)]; 277 #endif 278 279 printf("Board revision: "); 280 i2c_set_bus_num(1); 281 if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) 282 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); 283 else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) 284 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); 285 else { 286 printf("Unknown\n"); 287 rc = 1; 288 } 289 290 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR 291 i2c_set_bus_num(0); 292 293 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { 294 if (memcmp(data, eeprom_data, sizeof(data)) != 0) { 295 if (i2c_write 296 (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data, 297 sizeof(eeprom_data)) != 0) { 298 puts("Failure writing the HRCW to EEPROM via I2C.\n"); 299 rc = 1; 300 } 301 } 302 } else { 303 puts("Failure reading the HRCW from EEPROM via I2C.\n"); 304 rc = 1; 305 } 306 #endif 307 308 #ifdef CONFIG_SYS_I2C_RTC_ADDR 309 i2c_set_bus_num(1); 310 311 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) 312 == 0) { 313 314 /* Work-around for MPC8349E-mITX bug #13601. 315 If the RTC does not contain valid register values, the DS1339 316 Linux driver will not work. 317 */ 318 319 /* Make sure status register bits 6-2 are zero */ 320 ds1339_data[0x0f] &= ~0x7c; 321 322 /* Check for a valid day register value */ 323 ds1339_data[0x03] &= ~0xf8; 324 if (ds1339_data[0x03] == 0) { 325 ds1339_data[0x03] = 1; 326 } 327 328 /* Check for a valid date register value */ 329 ds1339_data[0x04] &= ~0xc0; 330 if ((ds1339_data[0x04] == 0) || 331 ((ds1339_data[0x04] & 0x0f) > 9) || 332 (ds1339_data[0x04] >= 0x32)) { 333 ds1339_data[0x04] = 1; 334 } 335 336 /* Check for a valid month register value */ 337 ds1339_data[0x05] &= ~0x60; 338 339 if ((ds1339_data[0x05] == 0) || 340 ((ds1339_data[0x05] & 0x0f) > 9) || 341 ((ds1339_data[0x05] >= 0x13) 342 && (ds1339_data[0x05] <= 0x19))) { 343 ds1339_data[0x05] = 1; 344 } 345 346 /* Enable Oscillator and rate select */ 347 ds1339_data[0x0e] = 0x1c; 348 349 /* Work-around for MPC8349E-mITX bug #13330. 350 Ensure that the RTC control register contains the value 0x1c. 351 This affects SATA performance. 352 */ 353 354 if (i2c_write 355 (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, 356 sizeof(ds1339_data))) { 357 puts("Failure writing to the RTC via I2C.\n"); 358 rc = 1; 359 } 360 } else { 361 puts("Failure reading from the RTC via I2C.\n"); 362 rc = 1; 363 } 364 #endif 365 366 i2c_set_bus_num(orig_bus); 367 #endif 368 369 #ifdef CONFIG_VSC7385_IMAGE 370 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, 371 CONFIG_VSC7385_IMAGE_SIZE)) { 372 puts("Failure uploading VSC7385 microcode.\n"); 373 rc = 1; 374 } 375 #endif 376 377 return rc; 378 } 379 380 #if defined(CONFIG_OF_BOARD_SETUP) 381 int ft_board_setup(void *blob, bd_t *bd) 382 { 383 ft_cpu_setup(blob, bd); 384 #ifdef CONFIG_PCI 385 ft_pci_setup(blob, bd); 386 #endif 387 388 return 0; 389 } 390 #endif 391