1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <ioports.h> 25 #include <mpc83xx.h> 26 #include <i2c.h> 27 #include <miiphy.h> 28 #include <vsc7385.h> 29 #ifdef CONFIG_PCI 30 #include <asm/mpc8349_pci.h> 31 #include <pci.h> 32 #endif 33 #include <spd_sdram.h> 34 #include <asm/mmu.h> 35 #if defined(CONFIG_OF_LIBFDT) 36 #include <libfdt.h> 37 #endif 38 39 #ifndef CONFIG_SPD_EEPROM 40 /************************************************************************* 41 * fixed sdram init -- doesn't use serial presence detect. 42 ************************************************************************/ 43 int fixed_sdram(void) 44 { 45 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 46 /* The size of RAM, in bytes */ 47 u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20; 48 u32 ddr_size_log2 = __ilog2(ddr_size); 49 50 im->sysconf.ddrlaw[0].ar = 51 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 52 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 53 54 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) 55 #warning Chip select bounds is only configurable in 16MB increments 56 #endif 57 im->ddr.csbnds[0].csbnds = 58 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | 59 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> 60 CSBNDS_EA_SHIFT) & CSBNDS_EA); 61 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; 62 63 /* Only one CS for DDR */ 64 im->ddr.cs_config[1] = 0; 65 im->ddr.cs_config[2] = 0; 66 im->ddr.cs_config[3] = 0; 67 68 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); 69 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); 70 71 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); 72 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); 73 74 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 75 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ 76 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; 77 im->ddr.sdram_mode = 78 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); 79 im->ddr.sdram_interval = 80 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << 81 SDRAM_INTERVAL_BSTOPRE_SHIFT); 82 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; 83 84 udelay(200); 85 86 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 87 88 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); 89 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); 90 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); 91 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); 92 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); 93 94 return CONFIG_SYS_DDR_SIZE; 95 } 96 #endif 97 98 #ifdef CONFIG_PCI 99 /* 100 * Initialize PCI Devices, report devices found 101 */ 102 #ifndef CONFIG_PCI_PNP 103 static struct pci_config_table pci_mpc83xxmitx_config_table[] = { 104 { 105 PCI_ANY_ID, 106 PCI_ANY_ID, 107 PCI_ANY_ID, 108 PCI_ANY_ID, 109 0x0f, 110 PCI_ANY_ID, 111 pci_cfgfunc_config_device, 112 { 113 PCI_ENET0_IOADDR, 114 PCI_ENET0_MEMADDR, 115 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} 116 }, 117 {} 118 } 119 #endif 120 121 volatile static struct pci_controller hose[] = { 122 { 123 #ifndef CONFIG_PCI_PNP 124 config_table:pci_mpc83xxmitx_config_table, 125 #endif 126 }, 127 { 128 #ifndef CONFIG_PCI_PNP 129 config_table:pci_mpc83xxmitx_config_table, 130 #endif 131 } 132 }; 133 #endif /* CONFIG_PCI */ 134 135 phys_size_t initdram(int board_type) 136 { 137 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 138 u32 msize = 0; 139 #ifdef CONFIG_DDR_ECC 140 volatile ddr83xx_t *ddr = &im->ddr; 141 #endif 142 143 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 144 return -1; 145 146 /* DDR SDRAM - Main SODIMM */ 147 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 148 #ifdef CONFIG_SPD_EEPROM 149 msize = spd_sdram(); 150 #else 151 msize = fixed_sdram(); 152 #endif 153 154 #ifdef CONFIG_DDR_ECC 155 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) 156 /* Unlike every other board, on the 83xx spd_sdram() returns 157 megabytes instead of just bytes. That's why we need to 158 multiple by 1MB when calling ddr_enable_ecc(). */ 159 ddr_enable_ecc(msize * 1048576); 160 #endif 161 162 /* return total bus RAM size(bytes) */ 163 return msize * 1024 * 1024; 164 } 165 166 int checkboard(void) 167 { 168 #ifdef CONFIG_MPC8349ITX 169 puts("Board: Freescale MPC8349E-mITX\n"); 170 #else 171 puts("Board: Freescale MPC8349E-mITX-GP\n"); 172 #endif 173 174 return 0; 175 } 176 177 /* 178 * Implement a work-around for a hardware problem with compact 179 * flash. 180 * 181 * Program the UPM if compact flash is enabled. 182 */ 183 int misc_init_f(void) 184 { 185 #ifdef CONFIG_VSC7385_ENET 186 volatile u32 *vsc7385_cpuctrl; 187 188 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up 189 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That 190 means it is 0 when the IRQ is not active. This makes the wire-AND 191 logic always assert IRQ7 to CPU even if there is no request from the 192 switch. Since the compact flash and the switch share the same IRQ, 193 the Linux kernel will think that the compact flash is requesting irq 194 and get stuck when it tries to clear the IRQ. Thus we need to set 195 the L2_IRQ0 and L2_IRQ1 to active low. 196 197 The following code sets the L1_IRQ and L2_IRQ polarity to active low. 198 Without this code, compact flash will not work in Linux because 199 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we 200 don't enable compact flash for U-Boot. 201 */ 202 203 vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0); 204 *vsc7385_cpuctrl |= 0x0c; 205 #endif 206 207 #ifdef CONFIG_COMPACT_FLASH 208 /* UPM Table Configuration Code */ 209 static uint UPMATable[] = { 210 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, 211 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, 212 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 213 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 214 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, 215 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 216 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, 217 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, 218 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 219 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 220 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 221 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 222 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 223 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 224 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 225 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 226 }; 227 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 228 229 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); 230 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); 231 232 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, 233 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 234 */ 235 immap->im_lbc.mamr = 0x08404440; 236 237 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); 238 239 puts("UPMA: Configured for compact flash\n"); 240 #endif 241 242 return 0; 243 } 244 245 /* 246 * Miscellaneous late-boot configurations 247 * 248 * Make sure the EEPROM has the HRCW correctly programmed. 249 * Make sure the RTC is correctly programmed. 250 * 251 * The MPC8349E-mITX can be configured to load the HRCW from 252 * EEPROM instead of flash. This is controlled via jumpers 253 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all 254 * jumpered), but if they're set to 001 or 010, then the HRCW is 255 * read from the "I2C EEPROM". 256 * 257 * This function makes sure that the I2C EEPROM is programmed 258 * correctly. 259 * 260 * If a VSC7385 microcode image is present, then upload it. 261 */ 262 int misc_init_r(void) 263 { 264 int rc = 0; 265 266 #ifdef CONFIG_HARD_I2C 267 268 unsigned int orig_bus = i2c_get_bus_num(); 269 u8 i2c_data; 270 271 #ifdef CONFIG_SYS_I2C_RTC_ADDR 272 u8 ds1339_data[17]; 273 #endif 274 275 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR 276 static u8 eeprom_data[] = /* HRCW data */ 277 { 278 0xAA, 0x55, 0xAA, /* Preamble */ 279 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ 280 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ 281 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF, 282 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF, 283 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF, 284 CONFIG_SYS_HRCW_LOW & 0xFF, 285 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ 286 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ 287 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF, 288 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF, 289 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF, 290 CONFIG_SYS_HRCW_HIGH & 0xFF 291 }; 292 293 u8 data[sizeof(eeprom_data)]; 294 #endif 295 296 printf("Board revision: "); 297 i2c_set_bus_num(1); 298 if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) 299 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); 300 else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) 301 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); 302 else { 303 printf("Unknown\n"); 304 rc = 1; 305 } 306 307 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR 308 i2c_set_bus_num(0); 309 310 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { 311 if (memcmp(data, eeprom_data, sizeof(data)) != 0) { 312 if (i2c_write 313 (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data, 314 sizeof(eeprom_data)) != 0) { 315 puts("Failure writing the HRCW to EEPROM via I2C.\n"); 316 rc = 1; 317 } 318 } 319 } else { 320 puts("Failure reading the HRCW from EEPROM via I2C.\n"); 321 rc = 1; 322 } 323 #endif 324 325 #ifdef CONFIG_SYS_I2C_RTC_ADDR 326 i2c_set_bus_num(1); 327 328 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) 329 == 0) { 330 331 /* Work-around for MPC8349E-mITX bug #13601. 332 If the RTC does not contain valid register values, the DS1339 333 Linux driver will not work. 334 */ 335 336 /* Make sure status register bits 6-2 are zero */ 337 ds1339_data[0x0f] &= ~0x7c; 338 339 /* Check for a valid day register value */ 340 ds1339_data[0x03] &= ~0xf8; 341 if (ds1339_data[0x03] == 0) { 342 ds1339_data[0x03] = 1; 343 } 344 345 /* Check for a valid date register value */ 346 ds1339_data[0x04] &= ~0xc0; 347 if ((ds1339_data[0x04] == 0) || 348 ((ds1339_data[0x04] & 0x0f) > 9) || 349 (ds1339_data[0x04] >= 0x32)) { 350 ds1339_data[0x04] = 1; 351 } 352 353 /* Check for a valid month register value */ 354 ds1339_data[0x05] &= ~0x60; 355 356 if ((ds1339_data[0x05] == 0) || 357 ((ds1339_data[0x05] & 0x0f) > 9) || 358 ((ds1339_data[0x05] >= 0x13) 359 && (ds1339_data[0x05] <= 0x19))) { 360 ds1339_data[0x05] = 1; 361 } 362 363 /* Enable Oscillator and rate select */ 364 ds1339_data[0x0e] = 0x1c; 365 366 /* Work-around for MPC8349E-mITX bug #13330. 367 Ensure that the RTC control register contains the value 0x1c. 368 This affects SATA performance. 369 */ 370 371 if (i2c_write 372 (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, 373 sizeof(ds1339_data))) { 374 puts("Failure writing to the RTC via I2C.\n"); 375 rc = 1; 376 } 377 } else { 378 puts("Failure reading from the RTC via I2C.\n"); 379 rc = 1; 380 } 381 #endif 382 383 i2c_set_bus_num(orig_bus); 384 #endif 385 386 #ifdef CONFIG_VSC7385_IMAGE 387 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, 388 CONFIG_VSC7385_IMAGE_SIZE)) { 389 puts("Failure uploading VSC7385 microcode.\n"); 390 rc = 1; 391 } 392 #endif 393 394 return rc; 395 } 396 397 #if defined(CONFIG_OF_BOARD_SETUP) 398 void ft_board_setup(void *blob, bd_t *bd) 399 { 400 ft_cpu_setup(blob, bd); 401 #ifdef CONFIG_PCI 402 ft_pci_setup(blob, bd); 403 #endif 404 } 405 #endif 406