1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <ioports.h>
9 #include <mpc83xx.h>
10 #include <i2c.h>
11 #include <miiphy.h>
12 #include <vsc7385.h>
13 #ifdef CONFIG_PCI
14 #include <asm/mpc8349_pci.h>
15 #include <pci.h>
16 #endif
17 #include <spd_sdram.h>
18 #include <asm/mmu.h>
19 #if defined(CONFIG_OF_LIBFDT)
20 #include <linux/libfdt.h>
21 #endif
22 
23 DECLARE_GLOBAL_DATA_PTR;
24 
25 #ifndef CONFIG_SPD_EEPROM
26 /*************************************************************************
27  *  fixed sdram init -- doesn't use serial presence detect.
28  ************************************************************************/
29 int fixed_sdram(void)
30 {
31 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
32 	/* The size of RAM, in bytes */
33 	u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
34 	u32 ddr_size_log2 = __ilog2(ddr_size);
35 
36 	im->sysconf.ddrlaw[0].ar =
37 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
38 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
39 
40 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
41 #warning Chip select bounds is only configurable in 16MB increments
42 #endif
43 	im->ddr.csbnds[0].csbnds =
44 		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
45 		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
46 				CSBNDS_EA_SHIFT) & CSBNDS_EA);
47 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
48 
49 	/* Only one CS for DDR */
50 	im->ddr.cs_config[1] = 0;
51 	im->ddr.cs_config[2] = 0;
52 	im->ddr.cs_config[3] = 0;
53 
54 	debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
55 	debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
56 
57 	debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
58 	debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
59 
60 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
61 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
62 	im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
63 	im->ddr.sdram_mode =
64 	    (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
65 	im->ddr.sdram_interval =
66 	    (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
67 						       SDRAM_INTERVAL_BSTOPRE_SHIFT);
68 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
69 
70 	udelay(200);
71 
72 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
73 
74 	debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
75 	debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
76 	debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
77 	debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
78 	debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
79 
80 	return CONFIG_SYS_DDR_SIZE;
81 }
82 #endif
83 
84 #ifdef CONFIG_PCI
85 /*
86  * Initialize PCI Devices, report devices found
87  */
88 #ifndef CONFIG_PCI_PNP
89 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
90 	{
91 	 PCI_ANY_ID,
92 	 PCI_ANY_ID,
93 	 PCI_ANY_ID,
94 	 PCI_ANY_ID,
95 	 0x0f,
96 	 PCI_ANY_ID,
97 	 pci_cfgfunc_config_device,
98 	 {
99 	  PCI_ENET0_IOADDR,
100 	  PCI_ENET0_MEMADDR,
101 	  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
102 	 },
103 	{}
104 }
105 #endif
106 
107 volatile static struct pci_controller hose[] = {
108 	{
109 #ifndef CONFIG_PCI_PNP
110 	      config_table:pci_mpc83xxmitx_config_table,
111 #endif
112 	 },
113 	{
114 #ifndef CONFIG_PCI_PNP
115 	      config_table:pci_mpc83xxmitx_config_table,
116 #endif
117 	 }
118 };
119 #endif				/* CONFIG_PCI */
120 
121 int dram_init(void)
122 {
123 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
124 	u32 msize = 0;
125 #ifdef CONFIG_DDR_ECC
126 	volatile ddr83xx_t *ddr = &im->ddr;
127 #endif
128 
129 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
130 		return -ENXIO;
131 
132 	/* DDR SDRAM - Main SODIMM */
133 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
134 #ifdef CONFIG_SPD_EEPROM
135 	msize = spd_sdram();
136 #else
137 	msize = fixed_sdram();
138 #endif
139 
140 #ifdef CONFIG_DDR_ECC
141 	if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
142 		/* Unlike every other board, on the 83xx spd_sdram() returns
143 		   megabytes instead of just bytes.  That's why we need to
144 		   multiple by 1MB when calling ddr_enable_ecc(). */
145 		ddr_enable_ecc(msize * 1048576);
146 #endif
147 
148 	/* return total bus RAM size(bytes) */
149 	gd->ram_size = msize * 1024 * 1024;
150 
151 	return 0;
152 }
153 
154 int checkboard(void)
155 {
156 #ifdef CONFIG_MPC8349ITX
157 	puts("Board: Freescale MPC8349E-mITX\n");
158 #else
159 	puts("Board: Freescale MPC8349E-mITX-GP\n");
160 #endif
161 
162 	return 0;
163 }
164 
165 /*
166  * Implement a work-around for a hardware problem with compact
167  * flash.
168  *
169  * Program the UPM if compact flash is enabled.
170  */
171 int misc_init_f(void)
172 {
173 #ifdef CONFIG_VSC7385_ENET
174 	volatile u32 *vsc7385_cpuctrl;
175 
176 	/* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register.  The power up
177 	   default of VSC7385 L1_IRQ and L2_IRQ requests are active high.  That
178 	   means it is 0 when the IRQ is not active.  This makes the wire-AND
179 	   logic always assert IRQ7 to CPU even if there is no request from the
180 	   switch.  Since the compact flash and the switch share the same IRQ,
181 	   the Linux kernel will think that the compact flash is requesting irq
182 	   and get stuck when it tries to clear the IRQ.  Thus we need to set
183 	   the L2_IRQ0 and L2_IRQ1 to active low.
184 
185 	   The following code sets the L1_IRQ and L2_IRQ polarity to active low.
186 	   Without this code, compact flash will not work in Linux because
187 	   unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
188 	   don't enable compact flash for U-Boot.
189 	 */
190 
191 	vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
192 	*vsc7385_cpuctrl |= 0x0c;
193 #endif
194 
195 #ifdef CONFIG_COMPACT_FLASH
196 	/* UPM Table Configuration Code */
197 	static uint UPMATable[] = {
198 		0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
199 		0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
200 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
201 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
202 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
203 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
204 		0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
205 		0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
206 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
207 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
208 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
209 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
210 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
211 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
212 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
213 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
214 	};
215 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
216 
217 	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
218 	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
219 
220 	/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
221 	   GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
222 	 */
223 	immap->im_lbc.mamr = 0x08404440;
224 
225 	upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
226 
227 	puts("UPMA:  Configured for compact flash\n");
228 #endif
229 
230 	return 0;
231 }
232 
233 /*
234  * Miscellaneous late-boot configurations
235  *
236  * Make sure the EEPROM has the HRCW correctly programmed.
237  * Make sure the RTC is correctly programmed.
238  *
239  * The MPC8349E-mITX can be configured to load the HRCW from
240  * EEPROM instead of flash.  This is controlled via jumpers
241  * LGPL0, 1, and 3.  Normally, these jumpers are set to 000 (all
242  * jumpered), but if they're set to 001 or 010, then the HRCW is
243  * read from the "I2C EEPROM".
244  *
245  * This function makes sure that the I2C EEPROM is programmed
246  * correctly.
247  *
248  * If a VSC7385 microcode image is present, then upload it.
249  */
250 int misc_init_r(void)
251 {
252 	int rc = 0;
253 
254 #if defined(CONFIG_SYS_I2C)
255 	unsigned int orig_bus = i2c_get_bus_num();
256 	u8 i2c_data;
257 
258 #ifdef CONFIG_SYS_I2C_RTC_ADDR
259 	u8 ds1339_data[17];
260 #endif
261 
262 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
263 	static u8 eeprom_data[] =	/* HRCW data */
264 	{
265 		0xAA, 0x55, 0xAA,       /* Preamble */
266 		0x7C,		        /* ACS=0, BYTE_EN=1111, CONT=1 */
267 		0x02, 0x40,	        /* RCWL ADDR=0x0_0900 */
268 		(CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
269 		(CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
270 		(CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
271 		CONFIG_SYS_HRCW_LOW & 0xFF,
272 		0x7C,		        /* ACS=0, BYTE_EN=1111, CONT=1 */
273 		0x02, 0x41,	        /* RCWH ADDR=0x0_0904 */
274 		(CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
275 		(CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
276 		(CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
277 		CONFIG_SYS_HRCW_HIGH & 0xFF
278 	};
279 
280 	u8 data[sizeof(eeprom_data)];
281 #endif
282 
283 	printf("Board revision: ");
284 	i2c_set_bus_num(1);
285 	if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
286 		printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
287 	else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
288 		printf("%u.%u (PCF8475)\n",  (i2c_data & 0x02) >> 1, i2c_data & 0x01);
289 	else {
290 		printf("Unknown\n");
291 		rc = 1;
292 	}
293 
294 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
295 	i2c_set_bus_num(0);
296 
297 	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
298 		if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
299 			if (i2c_write
300 			    (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
301 			     sizeof(eeprom_data)) != 0) {
302 				puts("Failure writing the HRCW to EEPROM via I2C.\n");
303 				rc = 1;
304 			}
305 		}
306 	} else {
307 		puts("Failure reading the HRCW from EEPROM via I2C.\n");
308 		rc = 1;
309 	}
310 #endif
311 
312 #ifdef CONFIG_SYS_I2C_RTC_ADDR
313 	i2c_set_bus_num(1);
314 
315 	if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
316 	    == 0) {
317 
318 		/* Work-around for MPC8349E-mITX bug #13601.
319 		   If the RTC does not contain valid register values, the DS1339
320 		   Linux driver will not work.
321 		 */
322 
323 		/* Make sure status register bits 6-2 are zero */
324 		ds1339_data[0x0f] &= ~0x7c;
325 
326 		/* Check for a valid day register value */
327 		ds1339_data[0x03] &= ~0xf8;
328 		if (ds1339_data[0x03] == 0) {
329 			ds1339_data[0x03] = 1;
330 		}
331 
332 		/* Check for a valid date register value */
333 		ds1339_data[0x04] &= ~0xc0;
334 		if ((ds1339_data[0x04] == 0) ||
335 		    ((ds1339_data[0x04] & 0x0f) > 9) ||
336 		    (ds1339_data[0x04] >= 0x32)) {
337 			ds1339_data[0x04] = 1;
338 		}
339 
340 		/* Check for a valid month register value */
341 		ds1339_data[0x05] &= ~0x60;
342 
343 		if ((ds1339_data[0x05] == 0) ||
344 		    ((ds1339_data[0x05] & 0x0f) > 9) ||
345 		    ((ds1339_data[0x05] >= 0x13)
346 		     && (ds1339_data[0x05] <= 0x19))) {
347 			ds1339_data[0x05] = 1;
348 		}
349 
350 		/* Enable Oscillator and rate select */
351 		ds1339_data[0x0e] = 0x1c;
352 
353 		/* Work-around for MPC8349E-mITX bug #13330.
354 		   Ensure that the RTC control register contains the value 0x1c.
355 		   This affects SATA performance.
356 		 */
357 
358 		if (i2c_write
359 		    (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
360 		     sizeof(ds1339_data))) {
361 			puts("Failure writing to the RTC via I2C.\n");
362 			rc = 1;
363 		}
364 	} else {
365 		puts("Failure reading from the RTC via I2C.\n");
366 		rc = 1;
367 	}
368 #endif
369 
370 	i2c_set_bus_num(orig_bus);
371 #endif
372 
373 #ifdef CONFIG_VSC7385_IMAGE
374 	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
375 		CONFIG_VSC7385_IMAGE_SIZE)) {
376 		puts("Failure uploading VSC7385 microcode.\n");
377 		rc = 1;
378 	}
379 #endif
380 
381 	return rc;
382 }
383 
384 #if defined(CONFIG_OF_BOARD_SETUP)
385 int ft_board_setup(void *blob, bd_t *bd)
386 {
387 	ft_cpu_setup(blob, bd);
388 #ifdef CONFIG_PCI
389 	ft_pci_setup(blob, bd);
390 #endif
391 
392 	return 0;
393 }
394 #endif
395