1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <ioports.h> 25 #include <mpc83xx.h> 26 #include <i2c.h> 27 #include <spd.h> 28 #include <miiphy.h> 29 30 #ifdef CONFIG_PCI 31 #include <asm/mpc8349_pci.h> 32 #include <pci.h> 33 #endif 34 35 #ifdef CONFIG_SPD_EEPROM 36 #include <spd_sdram.h> 37 #else 38 #include <asm/mmu.h> 39 #endif 40 #if defined(CONFIG_OF_FLAT_TREE) 41 #include <ft_build.h> 42 #elif defined(CONFIG_OF_LIBFDT) 43 #include <libfdt.h> 44 #endif 45 46 #ifndef CONFIG_SPD_EEPROM 47 /************************************************************************* 48 * fixed sdram init -- doesn't use serial presence detect. 49 ************************************************************************/ 50 int fixed_sdram(void) 51 { 52 volatile immap_t *im = (immap_t *) CFG_IMMR; 53 u32 ddr_size; /* The size of RAM, in bytes */ 54 u32 ddr_size_log2 = 0; 55 56 for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { 57 if (ddr_size & 1) { 58 return -1; 59 } 60 ddr_size_log2++; 61 } 62 63 im->sysconf.ddrlaw[0].ar = 64 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 65 im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff; 66 67 /* Only one CS0 for DDR */ 68 im->ddr.csbnds[0].csbnds = 0x0000000f; 69 im->ddr.cs_config[0] = CFG_DDR_CONFIG; 70 71 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); 72 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); 73 74 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); 75 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); 76 77 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 78 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ 79 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; 80 im->ddr.sdram_mode = 81 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); 82 im->ddr.sdram_interval = 83 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << 84 SDRAM_INTERVAL_BSTOPRE_SHIFT); 85 im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; 86 87 udelay(200); 88 89 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 90 91 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); 92 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); 93 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); 94 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); 95 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); 96 97 return CFG_DDR_SIZE; 98 } 99 #endif 100 101 #ifdef CONFIG_PCI 102 /* 103 * Initialize PCI Devices, report devices found 104 */ 105 #ifndef CONFIG_PCI_PNP 106 static struct pci_config_table pci_mpc83xxmitx_config_table[] = { 107 { 108 PCI_ANY_ID, 109 PCI_ANY_ID, 110 PCI_ANY_ID, 111 PCI_ANY_ID, 112 0x0f, 113 PCI_ANY_ID, 114 pci_cfgfunc_config_device, 115 { 116 PCI_ENET0_IOADDR, 117 PCI_ENET0_MEMADDR, 118 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} 119 }, 120 {} 121 } 122 #endif 123 124 volatile static struct pci_controller hose[] = { 125 { 126 #ifndef CONFIG_PCI_PNP 127 config_table:pci_mpc83xxmitx_config_table, 128 #endif 129 }, 130 { 131 #ifndef CONFIG_PCI_PNP 132 config_table:pci_mpc83xxmitx_config_table, 133 #endif 134 } 135 }; 136 #endif /* CONFIG_PCI */ 137 138 long int initdram(int board_type) 139 { 140 volatile immap_t *im = (immap_t *) CFG_IMMR; 141 u32 msize = 0; 142 #ifdef CONFIG_DDR_ECC 143 volatile ddr83xx_t *ddr = &im->ddr; 144 #endif 145 146 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 147 return -1; 148 149 /* DDR SDRAM - Main SODIMM */ 150 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; 151 #ifdef CONFIG_SPD_EEPROM 152 msize = spd_sdram(); 153 #else 154 msize = fixed_sdram(); 155 #endif 156 157 #ifdef CONFIG_DDR_ECC 158 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) 159 /* Unlike every other board, on the 83xx spd_sdram() returns 160 megabytes instead of just bytes. That's why we need to 161 multiple by 1MB when calling ddr_enable_ecc(). */ 162 ddr_enable_ecc(msize * 1048576); 163 #endif 164 165 /* return total bus RAM size(bytes) */ 166 return msize * 1024 * 1024; 167 } 168 169 int checkboard(void) 170 { 171 #ifdef CONFIG_MPC8349ITX 172 puts("Board: Freescale MPC8349E-mITX\n"); 173 #else 174 puts("Board: Freescale MPC8349E-mITX-GP\n"); 175 #endif 176 177 return 0; 178 } 179 180 /* 181 * Implement a work-around for a hardware problem with compact 182 * flash. 183 * 184 * Program the UPM if compact flash is enabled. 185 */ 186 int misc_init_f(void) 187 { 188 #ifdef CONFIG_VSC7385 189 volatile u32 *vsc7385_cpuctrl; 190 191 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up 192 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That 193 means it is 0 when the IRQ is not active. This makes the wire-AND 194 logic always assert IRQ7 to CPU even if there is no request from the 195 switch. Since the compact flash and the switch share the same IRQ, 196 the Linux kernel will think that the compact flash is requesting irq 197 and get stuck when it tries to clear the IRQ. Thus we need to set 198 the L2_IRQ0 and L2_IRQ1 to active low. 199 200 The following code sets the L1_IRQ and L2_IRQ polarity to active low. 201 Without this code, compact flash will not work in Linux because 202 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we 203 don't enable compact flash for U-Boot. 204 */ 205 206 vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); 207 *vsc7385_cpuctrl |= 0x0c; 208 #endif 209 210 #ifdef CONFIG_COMPACT_FLASH 211 /* UPM Table Configuration Code */ 212 static uint UPMATable[] = { 213 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, 214 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, 215 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 216 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 217 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, 218 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 219 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, 220 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, 221 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 222 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 223 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 224 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 225 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 226 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 227 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 228 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 229 }; 230 volatile immap_t *immap = (immap_t *) CFG_IMMR; 231 volatile lbus83xx_t *lbus = &immap->lbus; 232 233 lbus->bank[3].br = CFG_BR3_PRELIM; 234 lbus->bank[3].or = CFG_OR3_PRELIM; 235 236 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, 237 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 238 */ 239 lbus->mamr = 0x08404440; 240 241 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); 242 243 puts("UPMA: Configured for compact flash\n"); 244 #endif 245 246 return 0; 247 } 248 249 /* 250 * Make sure the EEPROM has the HRCW correctly programmed. 251 * Make sure the RTC is correctly programmed. 252 * 253 * The MPC8349E-mITX can be configured to load the HRCW from 254 * EEPROM instead of flash. This is controlled via jumpers 255 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all 256 * jumpered), but if they're set to 001 or 010, then the HRCW is 257 * read from the "I2C EEPROM". 258 * 259 * This function makes sure that the I2C EEPROM is programmed 260 * correctly. 261 */ 262 int misc_init_r(void) 263 { 264 int rc = 0; 265 266 #ifdef CONFIG_HARD_I2C 267 268 unsigned int orig_bus = i2c_get_bus_num(); 269 u8 i2c_data; 270 271 #ifdef CFG_I2C_RTC_ADDR 272 u8 ds1339_data[17]; 273 #endif 274 275 #ifdef CFG_I2C_EEPROM_ADDR 276 static u8 eeprom_data[] = /* HRCW data */ 277 { 278 0xAA, 0x55, 0xAA, /* Preamble */ 279 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ 280 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ 281 (CFG_HRCW_LOW >> 24) & 0xFF, 282 (CFG_HRCW_LOW >> 16) & 0xFF, 283 (CFG_HRCW_LOW >> 8) & 0xFF, 284 CFG_HRCW_LOW & 0xFF, 285 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ 286 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ 287 (CFG_HRCW_HIGH >> 24) & 0xFF, 288 (CFG_HRCW_HIGH >> 16) & 0xFF, 289 (CFG_HRCW_HIGH >> 8) & 0xFF, 290 CFG_HRCW_HIGH & 0xFF 291 }; 292 293 u8 data[sizeof(eeprom_data)]; 294 #endif 295 296 printf("Board revision: "); 297 i2c_set_bus_num(1); 298 if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) 299 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); 300 else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) 301 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); 302 else { 303 printf("Unknown\n"); 304 rc = 1; 305 } 306 307 #ifdef CFG_I2C_EEPROM_ADDR 308 i2c_set_bus_num(0); 309 310 if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { 311 if (memcmp(data, eeprom_data, sizeof(data)) != 0) { 312 if (i2c_write 313 (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data, 314 sizeof(eeprom_data)) != 0) { 315 puts("Failure writing the HRCW to EEPROM via I2C.\n"); 316 rc = 1; 317 } 318 } 319 } else { 320 puts("Failure reading the HRCW from EEPROM via I2C.\n"); 321 rc = 1; 322 } 323 #endif 324 325 #ifdef CFG_I2C_RTC_ADDR 326 i2c_set_bus_num(1); 327 328 if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) 329 == 0) { 330 331 /* Work-around for MPC8349E-mITX bug #13601. 332 If the RTC does not contain valid register values, the DS1339 333 Linux driver will not work. 334 */ 335 336 /* Make sure status register bits 6-2 are zero */ 337 ds1339_data[0x0f] &= ~0x7c; 338 339 /* Check for a valid day register value */ 340 ds1339_data[0x03] &= ~0xf8; 341 if (ds1339_data[0x03] == 0) { 342 ds1339_data[0x03] = 1; 343 } 344 345 /* Check for a valid date register value */ 346 ds1339_data[0x04] &= ~0xc0; 347 if ((ds1339_data[0x04] == 0) || 348 ((ds1339_data[0x04] & 0x0f) > 9) || 349 (ds1339_data[0x04] >= 0x32)) { 350 ds1339_data[0x04] = 1; 351 } 352 353 /* Check for a valid month register value */ 354 ds1339_data[0x05] &= ~0x60; 355 356 if ((ds1339_data[0x05] == 0) || 357 ((ds1339_data[0x05] & 0x0f) > 9) || 358 ((ds1339_data[0x05] >= 0x13) 359 && (ds1339_data[0x05] <= 0x19))) { 360 ds1339_data[0x05] = 1; 361 } 362 363 /* Enable Oscillator and rate select */ 364 ds1339_data[0x0e] = 0x1c; 365 366 /* Work-around for MPC8349E-mITX bug #13330. 367 Ensure that the RTC control register contains the value 0x1c. 368 This affects SATA performance. 369 */ 370 371 if (i2c_write 372 (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, 373 sizeof(ds1339_data))) { 374 puts("Failure writing to the RTC via I2C.\n"); 375 rc = 1; 376 } 377 } else { 378 puts("Failure reading from the RTC via I2C.\n"); 379 rc = 1; 380 } 381 #endif 382 383 i2c_set_bus_num(orig_bus); 384 #endif 385 386 return rc; 387 } 388 389 #if defined(CONFIG_OF_BOARD_SETUP) 390 void ft_board_setup(void *blob, bd_t *bd) 391 { 392 #if defined(CONFIG_OF_FLAT_TREE) 393 u32 *p; 394 int len; 395 396 p = ft_get_prop(blob, "/memory/reg", &len); 397 if (p != NULL) { 398 *p++ = cpu_to_be32(bd->bi_memstart); 399 *p = cpu_to_be32(bd->bi_memsize); 400 } 401 #endif 402 ft_cpu_setup(blob, bd); 403 #ifdef CONFIG_PCI 404 ft_pci_setup(blob, bd); 405 #endif 406 } 407 #endif 408