1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <ioports.h> 25 #include <mpc83xx.h> 26 #include <i2c.h> 27 #include <miiphy.h> 28 #include <vsc7385.h> 29 #ifdef CONFIG_PCI 30 #include <asm/mpc8349_pci.h> 31 #include <pci.h> 32 #endif 33 #include <spd_sdram.h> 34 #include <asm/mmu.h> 35 #if defined(CONFIG_OF_LIBFDT) 36 #include <libfdt.h> 37 #endif 38 39 #ifndef CONFIG_SPD_EEPROM 40 /************************************************************************* 41 * fixed sdram init -- doesn't use serial presence detect. 42 ************************************************************************/ 43 int fixed_sdram(void) 44 { 45 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 46 u32 ddr_size; /* The size of RAM, in bytes */ 47 u32 ddr_size_log2 = 0; 48 49 for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { 50 if (ddr_size & 1) { 51 return -1; 52 } 53 ddr_size_log2++; 54 } 55 56 im->sysconf.ddrlaw[0].ar = 57 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 58 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 59 60 /* Only one CS0 for DDR */ 61 im->ddr.csbnds[0].csbnds = 0x0000000f; 62 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; 63 64 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); 65 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); 66 67 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); 68 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); 69 70 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 71 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ 72 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; 73 im->ddr.sdram_mode = 74 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); 75 im->ddr.sdram_interval = 76 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << 77 SDRAM_INTERVAL_BSTOPRE_SHIFT); 78 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; 79 80 udelay(200); 81 82 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 83 84 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); 85 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); 86 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); 87 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); 88 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); 89 90 return CONFIG_SYS_DDR_SIZE; 91 } 92 #endif 93 94 #ifdef CONFIG_PCI 95 /* 96 * Initialize PCI Devices, report devices found 97 */ 98 #ifndef CONFIG_PCI_PNP 99 static struct pci_config_table pci_mpc83xxmitx_config_table[] = { 100 { 101 PCI_ANY_ID, 102 PCI_ANY_ID, 103 PCI_ANY_ID, 104 PCI_ANY_ID, 105 0x0f, 106 PCI_ANY_ID, 107 pci_cfgfunc_config_device, 108 { 109 PCI_ENET0_IOADDR, 110 PCI_ENET0_MEMADDR, 111 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} 112 }, 113 {} 114 } 115 #endif 116 117 volatile static struct pci_controller hose[] = { 118 { 119 #ifndef CONFIG_PCI_PNP 120 config_table:pci_mpc83xxmitx_config_table, 121 #endif 122 }, 123 { 124 #ifndef CONFIG_PCI_PNP 125 config_table:pci_mpc83xxmitx_config_table, 126 #endif 127 } 128 }; 129 #endif /* CONFIG_PCI */ 130 131 phys_size_t initdram(int board_type) 132 { 133 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 134 u32 msize = 0; 135 #ifdef CONFIG_DDR_ECC 136 volatile ddr83xx_t *ddr = &im->ddr; 137 #endif 138 139 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 140 return -1; 141 142 /* DDR SDRAM - Main SODIMM */ 143 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 144 #ifdef CONFIG_SPD_EEPROM 145 msize = spd_sdram(); 146 #else 147 msize = fixed_sdram(); 148 #endif 149 150 #ifdef CONFIG_DDR_ECC 151 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) 152 /* Unlike every other board, on the 83xx spd_sdram() returns 153 megabytes instead of just bytes. That's why we need to 154 multiple by 1MB when calling ddr_enable_ecc(). */ 155 ddr_enable_ecc(msize * 1048576); 156 #endif 157 158 /* return total bus RAM size(bytes) */ 159 return msize * 1024 * 1024; 160 } 161 162 int checkboard(void) 163 { 164 #ifdef CONFIG_MPC8349ITX 165 puts("Board: Freescale MPC8349E-mITX\n"); 166 #else 167 puts("Board: Freescale MPC8349E-mITX-GP\n"); 168 #endif 169 170 return 0; 171 } 172 173 /* 174 * Implement a work-around for a hardware problem with compact 175 * flash. 176 * 177 * Program the UPM if compact flash is enabled. 178 */ 179 int misc_init_f(void) 180 { 181 #ifdef CONFIG_VSC7385_ENET 182 volatile u32 *vsc7385_cpuctrl; 183 184 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up 185 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That 186 means it is 0 when the IRQ is not active. This makes the wire-AND 187 logic always assert IRQ7 to CPU even if there is no request from the 188 switch. Since the compact flash and the switch share the same IRQ, 189 the Linux kernel will think that the compact flash is requesting irq 190 and get stuck when it tries to clear the IRQ. Thus we need to set 191 the L2_IRQ0 and L2_IRQ1 to active low. 192 193 The following code sets the L1_IRQ and L2_IRQ polarity to active low. 194 Without this code, compact flash will not work in Linux because 195 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we 196 don't enable compact flash for U-Boot. 197 */ 198 199 vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0); 200 *vsc7385_cpuctrl |= 0x0c; 201 #endif 202 203 #ifdef CONFIG_COMPACT_FLASH 204 /* UPM Table Configuration Code */ 205 static uint UPMATable[] = { 206 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, 207 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, 208 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 209 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 210 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, 211 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 212 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, 213 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, 214 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 215 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 216 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 217 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 218 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 219 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 220 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 221 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 222 }; 223 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 224 225 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); 226 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); 227 228 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, 229 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 230 */ 231 immap->im_lbc.mamr = 0x08404440; 232 233 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); 234 235 puts("UPMA: Configured for compact flash\n"); 236 #endif 237 238 return 0; 239 } 240 241 /* 242 * Miscellaneous late-boot configurations 243 * 244 * Make sure the EEPROM has the HRCW correctly programmed. 245 * Make sure the RTC is correctly programmed. 246 * 247 * The MPC8349E-mITX can be configured to load the HRCW from 248 * EEPROM instead of flash. This is controlled via jumpers 249 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all 250 * jumpered), but if they're set to 001 or 010, then the HRCW is 251 * read from the "I2C EEPROM". 252 * 253 * This function makes sure that the I2C EEPROM is programmed 254 * correctly. 255 * 256 * If a VSC7385 microcode image is present, then upload it. 257 */ 258 int misc_init_r(void) 259 { 260 int rc = 0; 261 262 #ifdef CONFIG_HARD_I2C 263 264 unsigned int orig_bus = i2c_get_bus_num(); 265 u8 i2c_data; 266 267 #ifdef CONFIG_SYS_I2C_RTC_ADDR 268 u8 ds1339_data[17]; 269 #endif 270 271 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR 272 static u8 eeprom_data[] = /* HRCW data */ 273 { 274 0xAA, 0x55, 0xAA, /* Preamble */ 275 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ 276 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ 277 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF, 278 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF, 279 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF, 280 CONFIG_SYS_HRCW_LOW & 0xFF, 281 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ 282 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ 283 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF, 284 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF, 285 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF, 286 CONFIG_SYS_HRCW_HIGH & 0xFF 287 }; 288 289 u8 data[sizeof(eeprom_data)]; 290 #endif 291 292 printf("Board revision: "); 293 i2c_set_bus_num(1); 294 if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) 295 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); 296 else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) 297 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); 298 else { 299 printf("Unknown\n"); 300 rc = 1; 301 } 302 303 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR 304 i2c_set_bus_num(0); 305 306 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { 307 if (memcmp(data, eeprom_data, sizeof(data)) != 0) { 308 if (i2c_write 309 (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data, 310 sizeof(eeprom_data)) != 0) { 311 puts("Failure writing the HRCW to EEPROM via I2C.\n"); 312 rc = 1; 313 } 314 } 315 } else { 316 puts("Failure reading the HRCW from EEPROM via I2C.\n"); 317 rc = 1; 318 } 319 #endif 320 321 #ifdef CONFIG_SYS_I2C_RTC_ADDR 322 i2c_set_bus_num(1); 323 324 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) 325 == 0) { 326 327 /* Work-around for MPC8349E-mITX bug #13601. 328 If the RTC does not contain valid register values, the DS1339 329 Linux driver will not work. 330 */ 331 332 /* Make sure status register bits 6-2 are zero */ 333 ds1339_data[0x0f] &= ~0x7c; 334 335 /* Check for a valid day register value */ 336 ds1339_data[0x03] &= ~0xf8; 337 if (ds1339_data[0x03] == 0) { 338 ds1339_data[0x03] = 1; 339 } 340 341 /* Check for a valid date register value */ 342 ds1339_data[0x04] &= ~0xc0; 343 if ((ds1339_data[0x04] == 0) || 344 ((ds1339_data[0x04] & 0x0f) > 9) || 345 (ds1339_data[0x04] >= 0x32)) { 346 ds1339_data[0x04] = 1; 347 } 348 349 /* Check for a valid month register value */ 350 ds1339_data[0x05] &= ~0x60; 351 352 if ((ds1339_data[0x05] == 0) || 353 ((ds1339_data[0x05] & 0x0f) > 9) || 354 ((ds1339_data[0x05] >= 0x13) 355 && (ds1339_data[0x05] <= 0x19))) { 356 ds1339_data[0x05] = 1; 357 } 358 359 /* Enable Oscillator and rate select */ 360 ds1339_data[0x0e] = 0x1c; 361 362 /* Work-around for MPC8349E-mITX bug #13330. 363 Ensure that the RTC control register contains the value 0x1c. 364 This affects SATA performance. 365 */ 366 367 if (i2c_write 368 (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, 369 sizeof(ds1339_data))) { 370 puts("Failure writing to the RTC via I2C.\n"); 371 rc = 1; 372 } 373 } else { 374 puts("Failure reading from the RTC via I2C.\n"); 375 rc = 1; 376 } 377 #endif 378 379 i2c_set_bus_num(orig_bus); 380 #endif 381 382 #ifdef CONFIG_VSC7385_IMAGE 383 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, 384 CONFIG_VSC7385_IMAGE_SIZE)) { 385 puts("Failure uploading VSC7385 microcode.\n"); 386 rc = 1; 387 } 388 #endif 389 390 return rc; 391 } 392 393 #if defined(CONFIG_OF_BOARD_SETUP) 394 void ft_board_setup(void *blob, bd_t *bd) 395 { 396 ft_cpu_setup(blob, bd); 397 #ifdef CONFIG_PCI 398 ft_pci_setup(blob, bd); 399 #endif 400 } 401 #endif 402