1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <ioports.h> 25 #include <mpc83xx.h> 26 #include <i2c.h> 27 #include <spd.h> 28 #include <miiphy.h> 29 30 #ifdef CONFIG_PCI 31 #include <asm/mpc8349_pci.h> 32 #include <pci.h> 33 #endif 34 35 #ifdef CONFIG_SPD_EEPROM 36 #include <spd_sdram.h> 37 #else 38 #include <asm/mmu.h> 39 #endif 40 #if defined(CONFIG_OF_LIBFDT) 41 #include <libfdt.h> 42 #endif 43 44 #ifndef CONFIG_SPD_EEPROM 45 /************************************************************************* 46 * fixed sdram init -- doesn't use serial presence detect. 47 ************************************************************************/ 48 int fixed_sdram(void) 49 { 50 volatile immap_t *im = (immap_t *) CFG_IMMR; 51 u32 ddr_size; /* The size of RAM, in bytes */ 52 u32 ddr_size_log2 = 0; 53 54 for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { 55 if (ddr_size & 1) { 56 return -1; 57 } 58 ddr_size_log2++; 59 } 60 61 im->sysconf.ddrlaw[0].ar = 62 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 63 im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff; 64 65 /* Only one CS0 for DDR */ 66 im->ddr.csbnds[0].csbnds = 0x0000000f; 67 im->ddr.cs_config[0] = CFG_DDR_CONFIG; 68 69 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); 70 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); 71 72 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); 73 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); 74 75 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 76 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ 77 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; 78 im->ddr.sdram_mode = 79 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); 80 im->ddr.sdram_interval = 81 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << 82 SDRAM_INTERVAL_BSTOPRE_SHIFT); 83 im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; 84 85 udelay(200); 86 87 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 88 89 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); 90 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); 91 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); 92 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); 93 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); 94 95 return CFG_DDR_SIZE; 96 } 97 #endif 98 99 #ifdef CONFIG_PCI 100 /* 101 * Initialize PCI Devices, report devices found 102 */ 103 #ifndef CONFIG_PCI_PNP 104 static struct pci_config_table pci_mpc83xxmitx_config_table[] = { 105 { 106 PCI_ANY_ID, 107 PCI_ANY_ID, 108 PCI_ANY_ID, 109 PCI_ANY_ID, 110 0x0f, 111 PCI_ANY_ID, 112 pci_cfgfunc_config_device, 113 { 114 PCI_ENET0_IOADDR, 115 PCI_ENET0_MEMADDR, 116 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} 117 }, 118 {} 119 } 120 #endif 121 122 volatile static struct pci_controller hose[] = { 123 { 124 #ifndef CONFIG_PCI_PNP 125 config_table:pci_mpc83xxmitx_config_table, 126 #endif 127 }, 128 { 129 #ifndef CONFIG_PCI_PNP 130 config_table:pci_mpc83xxmitx_config_table, 131 #endif 132 } 133 }; 134 #endif /* CONFIG_PCI */ 135 136 long int initdram(int board_type) 137 { 138 volatile immap_t *im = (immap_t *) CFG_IMMR; 139 u32 msize = 0; 140 #ifdef CONFIG_DDR_ECC 141 volatile ddr83xx_t *ddr = &im->ddr; 142 #endif 143 144 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 145 return -1; 146 147 /* DDR SDRAM - Main SODIMM */ 148 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; 149 #ifdef CONFIG_SPD_EEPROM 150 msize = spd_sdram(); 151 #else 152 msize = fixed_sdram(); 153 #endif 154 155 #ifdef CONFIG_DDR_ECC 156 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) 157 /* Unlike every other board, on the 83xx spd_sdram() returns 158 megabytes instead of just bytes. That's why we need to 159 multiple by 1MB when calling ddr_enable_ecc(). */ 160 ddr_enable_ecc(msize * 1048576); 161 #endif 162 163 /* return total bus RAM size(bytes) */ 164 return msize * 1024 * 1024; 165 } 166 167 int checkboard(void) 168 { 169 #ifdef CONFIG_MPC8349ITX 170 puts("Board: Freescale MPC8349E-mITX\n"); 171 #else 172 puts("Board: Freescale MPC8349E-mITX-GP\n"); 173 #endif 174 175 return 0; 176 } 177 178 /* 179 * Implement a work-around for a hardware problem with compact 180 * flash. 181 * 182 * Program the UPM if compact flash is enabled. 183 */ 184 int misc_init_f(void) 185 { 186 #ifdef CONFIG_VSC7385 187 volatile u32 *vsc7385_cpuctrl; 188 189 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up 190 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That 191 means it is 0 when the IRQ is not active. This makes the wire-AND 192 logic always assert IRQ7 to CPU even if there is no request from the 193 switch. Since the compact flash and the switch share the same IRQ, 194 the Linux kernel will think that the compact flash is requesting irq 195 and get stuck when it tries to clear the IRQ. Thus we need to set 196 the L2_IRQ0 and L2_IRQ1 to active low. 197 198 The following code sets the L1_IRQ and L2_IRQ polarity to active low. 199 Without this code, compact flash will not work in Linux because 200 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we 201 don't enable compact flash for U-Boot. 202 */ 203 204 vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); 205 *vsc7385_cpuctrl |= 0x0c; 206 #endif 207 208 #ifdef CONFIG_COMPACT_FLASH 209 /* UPM Table Configuration Code */ 210 static uint UPMATable[] = { 211 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, 212 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, 213 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 214 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 215 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, 216 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 217 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, 218 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, 219 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 220 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 221 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 222 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 223 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 224 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, 225 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 226 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 227 }; 228 volatile immap_t *immap = (immap_t *) CFG_IMMR; 229 volatile lbus83xx_t *lbus = &immap->lbus; 230 231 lbus->bank[3].br = CFG_BR3_PRELIM; 232 lbus->bank[3].or = CFG_OR3_PRELIM; 233 234 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, 235 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 236 */ 237 lbus->mamr = 0x08404440; 238 239 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); 240 241 puts("UPMA: Configured for compact flash\n"); 242 #endif 243 244 return 0; 245 } 246 247 /* 248 * Make sure the EEPROM has the HRCW correctly programmed. 249 * Make sure the RTC is correctly programmed. 250 * 251 * The MPC8349E-mITX can be configured to load the HRCW from 252 * EEPROM instead of flash. This is controlled via jumpers 253 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all 254 * jumpered), but if they're set to 001 or 010, then the HRCW is 255 * read from the "I2C EEPROM". 256 * 257 * This function makes sure that the I2C EEPROM is programmed 258 * correctly. 259 */ 260 int misc_init_r(void) 261 { 262 int rc = 0; 263 264 #ifdef CONFIG_HARD_I2C 265 266 unsigned int orig_bus = i2c_get_bus_num(); 267 u8 i2c_data; 268 269 #ifdef CFG_I2C_RTC_ADDR 270 u8 ds1339_data[17]; 271 #endif 272 273 #ifdef CFG_I2C_EEPROM_ADDR 274 static u8 eeprom_data[] = /* HRCW data */ 275 { 276 0xAA, 0x55, 0xAA, /* Preamble */ 277 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ 278 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ 279 (CFG_HRCW_LOW >> 24) & 0xFF, 280 (CFG_HRCW_LOW >> 16) & 0xFF, 281 (CFG_HRCW_LOW >> 8) & 0xFF, 282 CFG_HRCW_LOW & 0xFF, 283 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ 284 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ 285 (CFG_HRCW_HIGH >> 24) & 0xFF, 286 (CFG_HRCW_HIGH >> 16) & 0xFF, 287 (CFG_HRCW_HIGH >> 8) & 0xFF, 288 CFG_HRCW_HIGH & 0xFF 289 }; 290 291 u8 data[sizeof(eeprom_data)]; 292 #endif 293 294 printf("Board revision: "); 295 i2c_set_bus_num(1); 296 if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) 297 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); 298 else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) 299 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); 300 else { 301 printf("Unknown\n"); 302 rc = 1; 303 } 304 305 #ifdef CFG_I2C_EEPROM_ADDR 306 i2c_set_bus_num(0); 307 308 if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { 309 if (memcmp(data, eeprom_data, sizeof(data)) != 0) { 310 if (i2c_write 311 (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data, 312 sizeof(eeprom_data)) != 0) { 313 puts("Failure writing the HRCW to EEPROM via I2C.\n"); 314 rc = 1; 315 } 316 } 317 } else { 318 puts("Failure reading the HRCW from EEPROM via I2C.\n"); 319 rc = 1; 320 } 321 #endif 322 323 #ifdef CFG_I2C_RTC_ADDR 324 i2c_set_bus_num(1); 325 326 if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) 327 == 0) { 328 329 /* Work-around for MPC8349E-mITX bug #13601. 330 If the RTC does not contain valid register values, the DS1339 331 Linux driver will not work. 332 */ 333 334 /* Make sure status register bits 6-2 are zero */ 335 ds1339_data[0x0f] &= ~0x7c; 336 337 /* Check for a valid day register value */ 338 ds1339_data[0x03] &= ~0xf8; 339 if (ds1339_data[0x03] == 0) { 340 ds1339_data[0x03] = 1; 341 } 342 343 /* Check for a valid date register value */ 344 ds1339_data[0x04] &= ~0xc0; 345 if ((ds1339_data[0x04] == 0) || 346 ((ds1339_data[0x04] & 0x0f) > 9) || 347 (ds1339_data[0x04] >= 0x32)) { 348 ds1339_data[0x04] = 1; 349 } 350 351 /* Check for a valid month register value */ 352 ds1339_data[0x05] &= ~0x60; 353 354 if ((ds1339_data[0x05] == 0) || 355 ((ds1339_data[0x05] & 0x0f) > 9) || 356 ((ds1339_data[0x05] >= 0x13) 357 && (ds1339_data[0x05] <= 0x19))) { 358 ds1339_data[0x05] = 1; 359 } 360 361 /* Enable Oscillator and rate select */ 362 ds1339_data[0x0e] = 0x1c; 363 364 /* Work-around for MPC8349E-mITX bug #13330. 365 Ensure that the RTC control register contains the value 0x1c. 366 This affects SATA performance. 367 */ 368 369 if (i2c_write 370 (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, 371 sizeof(ds1339_data))) { 372 puts("Failure writing to the RTC via I2C.\n"); 373 rc = 1; 374 } 375 } else { 376 puts("Failure reading from the RTC via I2C.\n"); 377 rc = 1; 378 } 379 #endif 380 381 i2c_set_bus_num(orig_bus); 382 #endif 383 384 return rc; 385 } 386 387 #if defined(CONFIG_OF_BOARD_SETUP) 388 void ft_board_setup(void *blob, bd_t *bd) 389 { 390 ft_cpu_setup(blob, bd); 391 #ifdef CONFIG_PCI 392 ft_pci_setup(blob, bd); 393 #endif 394 } 395 #endif 396