1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 */
5
6 #include <common.h>
7 #include <ioports.h>
8 #include <mpc83xx.h>
9 #include <i2c.h>
10 #include <miiphy.h>
11 #include <vsc7385.h>
12 #ifdef CONFIG_PCI
13 #include <asm/mpc8349_pci.h>
14 #include <pci.h>
15 #endif
16 #include <spd_sdram.h>
17 #include <asm/mmu.h>
18 #if defined(CONFIG_OF_LIBFDT)
19 #include <linux/libfdt.h>
20 #endif
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 #ifndef CONFIG_SPD_EEPROM
25 /*************************************************************************
26 * fixed sdram init -- doesn't use serial presence detect.
27 ************************************************************************/
fixed_sdram(void)28 int fixed_sdram(void)
29 {
30 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
31 /* The size of RAM, in bytes */
32 u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
33 u32 ddr_size_log2 = __ilog2(ddr_size);
34
35 im->sysconf.ddrlaw[0].ar =
36 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
37 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
38
39 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
40 #warning Chip select bounds is only configurable in 16MB increments
41 #endif
42 im->ddr.csbnds[0].csbnds =
43 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
44 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
45 CSBNDS_EA_SHIFT) & CSBNDS_EA);
46 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
47
48 /* Only one CS for DDR */
49 im->ddr.cs_config[1] = 0;
50 im->ddr.cs_config[2] = 0;
51 im->ddr.cs_config[3] = 0;
52
53 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
54 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
55
56 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
57 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
58
59 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
60 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
61 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
62 im->ddr.sdram_mode =
63 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
64 im->ddr.sdram_interval =
65 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
66 SDRAM_INTERVAL_BSTOPRE_SHIFT);
67 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
68
69 udelay(200);
70
71 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
72
73 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
74 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
75 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
76 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
77 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
78
79 return CONFIG_SYS_DDR_SIZE;
80 }
81 #endif
82
83 #ifdef CONFIG_PCI
84 /*
85 * Initialize PCI Devices, report devices found
86 */
87 #ifndef CONFIG_PCI_PNP
88 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
89 {
90 PCI_ANY_ID,
91 PCI_ANY_ID,
92 PCI_ANY_ID,
93 PCI_ANY_ID,
94 0x0f,
95 PCI_ANY_ID,
96 pci_cfgfunc_config_device,
97 {
98 PCI_ENET0_IOADDR,
99 PCI_ENET0_MEMADDR,
100 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
101 },
102 {}
103 }
104 #endif
105
106 volatile static struct pci_controller hose[] = {
107 {
108 #ifndef CONFIG_PCI_PNP
109 config_table:pci_mpc83xxmitx_config_table,
110 #endif
111 },
112 {
113 #ifndef CONFIG_PCI_PNP
114 config_table:pci_mpc83xxmitx_config_table,
115 #endif
116 }
117 };
118 #endif /* CONFIG_PCI */
119
dram_init(void)120 int dram_init(void)
121 {
122 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
123 u32 msize = 0;
124 #ifdef CONFIG_DDR_ECC
125 volatile ddr83xx_t *ddr = &im->ddr;
126 #endif
127
128 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
129 return -ENXIO;
130
131 /* DDR SDRAM - Main SODIMM */
132 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
133 #ifdef CONFIG_SPD_EEPROM
134 msize = spd_sdram();
135 #else
136 msize = fixed_sdram();
137 #endif
138
139 #ifdef CONFIG_DDR_ECC
140 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
141 /* Unlike every other board, on the 83xx spd_sdram() returns
142 megabytes instead of just bytes. That's why we need to
143 multiple by 1MB when calling ddr_enable_ecc(). */
144 ddr_enable_ecc(msize * 1048576);
145 #endif
146
147 /* return total bus RAM size(bytes) */
148 gd->ram_size = msize * 1024 * 1024;
149
150 return 0;
151 }
152
checkboard(void)153 int checkboard(void)
154 {
155 #ifdef CONFIG_MPC8349ITX
156 puts("Board: Freescale MPC8349E-mITX\n");
157 #else
158 puts("Board: Freescale MPC8349E-mITX-GP\n");
159 #endif
160
161 return 0;
162 }
163
164 /*
165 * Implement a work-around for a hardware problem with compact
166 * flash.
167 *
168 * Program the UPM if compact flash is enabled.
169 */
misc_init_f(void)170 int misc_init_f(void)
171 {
172 #ifdef CONFIG_VSC7385_ENET
173 volatile u32 *vsc7385_cpuctrl;
174
175 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
176 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
177 means it is 0 when the IRQ is not active. This makes the wire-AND
178 logic always assert IRQ7 to CPU even if there is no request from the
179 switch. Since the compact flash and the switch share the same IRQ,
180 the Linux kernel will think that the compact flash is requesting irq
181 and get stuck when it tries to clear the IRQ. Thus we need to set
182 the L2_IRQ0 and L2_IRQ1 to active low.
183
184 The following code sets the L1_IRQ and L2_IRQ polarity to active low.
185 Without this code, compact flash will not work in Linux because
186 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
187 don't enable compact flash for U-Boot.
188 */
189
190 vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
191 *vsc7385_cpuctrl |= 0x0c;
192 #endif
193
194 #ifdef CONFIG_COMPACT_FLASH
195 /* UPM Table Configuration Code */
196 static uint UPMATable[] = {
197 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
198 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
199 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
200 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
201 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
202 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
203 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
204 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
205 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
206 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
207 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
208 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
209 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
210 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
211 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
212 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
213 };
214 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
215
216 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
217 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
218
219 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
220 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
221 */
222 immap->im_lbc.mamr = 0x08404440;
223
224 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
225
226 puts("UPMA: Configured for compact flash\n");
227 #endif
228
229 return 0;
230 }
231
232 /*
233 * Miscellaneous late-boot configurations
234 *
235 * Make sure the EEPROM has the HRCW correctly programmed.
236 * Make sure the RTC is correctly programmed.
237 *
238 * The MPC8349E-mITX can be configured to load the HRCW from
239 * EEPROM instead of flash. This is controlled via jumpers
240 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
241 * jumpered), but if they're set to 001 or 010, then the HRCW is
242 * read from the "I2C EEPROM".
243 *
244 * This function makes sure that the I2C EEPROM is programmed
245 * correctly.
246 *
247 * If a VSC7385 microcode image is present, then upload it.
248 */
misc_init_r(void)249 int misc_init_r(void)
250 {
251 int rc = 0;
252
253 #if defined(CONFIG_SYS_I2C)
254 unsigned int orig_bus = i2c_get_bus_num();
255 u8 i2c_data;
256
257 #ifdef CONFIG_SYS_I2C_RTC_ADDR
258 u8 ds1339_data[17];
259 #endif
260
261 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
262 static u8 eeprom_data[] = /* HRCW data */
263 {
264 0xAA, 0x55, 0xAA, /* Preamble */
265 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
266 0x02, 0x40, /* RCWL ADDR=0x0_0900 */
267 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
268 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
269 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
270 CONFIG_SYS_HRCW_LOW & 0xFF,
271 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
272 0x02, 0x41, /* RCWH ADDR=0x0_0904 */
273 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
274 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
275 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
276 CONFIG_SYS_HRCW_HIGH & 0xFF
277 };
278
279 u8 data[sizeof(eeprom_data)];
280 #endif
281
282 printf("Board revision: ");
283 i2c_set_bus_num(1);
284 if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
285 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
286 else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
287 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
288 else {
289 printf("Unknown\n");
290 rc = 1;
291 }
292
293 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
294 i2c_set_bus_num(0);
295
296 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
297 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
298 if (i2c_write
299 (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
300 sizeof(eeprom_data)) != 0) {
301 puts("Failure writing the HRCW to EEPROM via I2C.\n");
302 rc = 1;
303 }
304 }
305 } else {
306 puts("Failure reading the HRCW from EEPROM via I2C.\n");
307 rc = 1;
308 }
309 #endif
310
311 #ifdef CONFIG_SYS_I2C_RTC_ADDR
312 i2c_set_bus_num(1);
313
314 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
315 == 0) {
316
317 /* Work-around for MPC8349E-mITX bug #13601.
318 If the RTC does not contain valid register values, the DS1339
319 Linux driver will not work.
320 */
321
322 /* Make sure status register bits 6-2 are zero */
323 ds1339_data[0x0f] &= ~0x7c;
324
325 /* Check for a valid day register value */
326 ds1339_data[0x03] &= ~0xf8;
327 if (ds1339_data[0x03] == 0) {
328 ds1339_data[0x03] = 1;
329 }
330
331 /* Check for a valid date register value */
332 ds1339_data[0x04] &= ~0xc0;
333 if ((ds1339_data[0x04] == 0) ||
334 ((ds1339_data[0x04] & 0x0f) > 9) ||
335 (ds1339_data[0x04] >= 0x32)) {
336 ds1339_data[0x04] = 1;
337 }
338
339 /* Check for a valid month register value */
340 ds1339_data[0x05] &= ~0x60;
341
342 if ((ds1339_data[0x05] == 0) ||
343 ((ds1339_data[0x05] & 0x0f) > 9) ||
344 ((ds1339_data[0x05] >= 0x13)
345 && (ds1339_data[0x05] <= 0x19))) {
346 ds1339_data[0x05] = 1;
347 }
348
349 /* Enable Oscillator and rate select */
350 ds1339_data[0x0e] = 0x1c;
351
352 /* Work-around for MPC8349E-mITX bug #13330.
353 Ensure that the RTC control register contains the value 0x1c.
354 This affects SATA performance.
355 */
356
357 if (i2c_write
358 (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
359 sizeof(ds1339_data))) {
360 puts("Failure writing to the RTC via I2C.\n");
361 rc = 1;
362 }
363 } else {
364 puts("Failure reading from the RTC via I2C.\n");
365 rc = 1;
366 }
367 #endif
368
369 i2c_set_bus_num(orig_bus);
370 #endif
371
372 #ifdef CONFIG_VSC7385_IMAGE
373 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
374 CONFIG_VSC7385_IMAGE_SIZE)) {
375 puts("Failure uploading VSC7385 microcode.\n");
376 rc = 1;
377 }
378 #endif
379
380 return rc;
381 }
382
383 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)384 int ft_board_setup(void *blob, bd_t *bd)
385 {
386 ft_cpu_setup(blob, bd);
387 #ifdef CONFIG_PCI
388 ft_pci_setup(blob, bd);
389 #endif
390
391 return 0;
392 }
393 #endif
394