1Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards 2--------------------------------------------------- 3 41. Board Description 5 6 The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring 7 the Freescale MPC8349E processor in a Mini-ITX form factor. 8 9 The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences: 10 11 A) One 8MB on-board flash EEPROM chip, instead of two. 12 B) No SATA controller 13 C) No Compact Flash slot 14 D) No Mini-PCI slot 15 E) No Vitesse 7385 5-port Ethernet switch 16 F) No 4-port USB Type-A interface 17 182. Board Switches and Jumpers 19 202.0 Descriptions for all of the board jumpers can be found in the User 21 Guide. Of particular interest to U-Boot developers is jumper J22: 22 23 Pos. Name Default Description 24 ----------------------------------------------------------------------- 25 A LGPL0 ON (0) HRCW source, bit 0 26 B LGPL1 ON (0) HRCW source, bit 1 27 C LGPL3 ON (0) HRCW source, bit 2 28 D LGPL5 OFF (1) PCI_SYNC_OUT frequency 29 E BOOT1 ON (0) Flash EEPROM boot device 30 F PCI_M66EN ON (0) PCI 66MHz enable 31 G I2C-WP ON (0) I2C EEPROM write protection 32 H F_WP OFF (1) Flash EEPROM write protection 33 34 Jumper J22.E is only for the ITX, and it decides the configuration 35 of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip 36 U4 is located at address FE000000 and flash chip U7 is at FE800000. 37 If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000. 38 39 For U-Boot development, J22.E can be used to switch back-and-forth 40 between two U-Boot images. 41 423. Memory Map 43 443.1. The memory map should look pretty much like this: 45 46 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB) 47 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB) 48 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB) 49 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB) 50 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB) 51 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB) 52 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only) 53 0xF001_0000 - 0xF001_FFFF Local bus expansion slot 54 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only) 55 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory 56 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only) 57 583.2 Flash EEPROM layout. 59 60 On the ITX, jumper J22.E is used to determine which flash chips are 61 at which address. When J22.E is switched, addresses from FE000000 62 to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF. 63 64 On the ITX, at the normal boot address (aka HIGHBOOT): 65 66 FE00_0000 HRCW 67 FE70_0000 Alternative U-Boot image 68 FE80_0000 Alternative HRCW 69 FEF0_0000 U-Boot image 70 FEFF_FFFF End of flash 71 72 On the ITX, at the low boot address (LOWBOOT) 73 74 FE00_0000 HRCW and U-Boot image 75 FE04_0000 U-Boot environment variables 76 FE80_0000 Alternative HRCW and U-Boot image 77 FEFF_FFFF End of flash 78 79 On the ITX-GP, the only option is LOWBOOT and there is only one chip 80 81 FE00_0000 HRCW and U-Boot image 82 FE04_0000 U-Boot environment variables 83 F7FF_FFFF End of flash 84 854. Definitions 86 874.1 Explanation of NEW definitions in: 88 89 include/configs/MPC8349ITX.h 90 91 CONFIG_MPC83xx MPC83xx family 92 CONFIG_MPC8349 MPC8349 specific 93 CONFIG_MPC8349ITX MPC8349E-mITX 94 CONFIG_MPC8349ITXGP MPC8349E-mITX-GP 95 965. Compilation 97 98 Assuming you're using BASH shell: 99 100 export CROSS_COMPILE=your-cross-compile-prefix 101 cd u-boot 102 make distclean 103 104 make MPC8349ITX_config 105 or: 106 make MPC8349ITXGP_config 107 or: 108 make MPC8349ITX_LOWBOOT_config 109 110 make 111 1126. Downloading and Flashing Images 113 1146.1 Download via tftp: 115 116 tftp $loadaddr <uboot> 117 118 where "<uboot>" is the path and filename, on the TFTP server, of 119 the U-Boot image. 120 1216.1 Reflash U-Boot Image using U-Boot 122 123 setenv uboot <uboot> 124 run tftpflash 125 126 where "<uboot>" is the path and filename, on the TFTP server, of 127 the U-Boot image. 128 1296.2 Using the HRCW to switch between two different U-Boot images on the ITX 130 131 Because the ITX has 16MB of flash, it is possible to keep two U-Boot 132 images in flash, and use the HRCW to specify which one is to be used 133 when the board boots. This trick is especially effective with a 134 hardware debugger that can override the HRCW, such as the BDI-2000. 135 136 When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image 137 at address FE000000. When the BMS bit is 1, the ITX will boot the 138 image at address FEF00000. 139 140 Therefore, just put a U-Boot image at both FE000000 and FEF00000 and 141 change the BMS bit whenever you want to boot the other image. 142 143 Step-by-step instructions: 144 145 1) Build an ITX image to be loaded at FEF00000 146 147 make distclean 148 make MPC8349ITX_config 149 make 150 151 2) Take the u-boot.bin image and flash it at FEF00000. 152 153 tftp $loadaddr u-boot.bin 154 protect off all 155 erase FEF00000 +$filesize 156 cp.b $loadaddr FEF00000 $filesize 157 158 3) Build an ITX image to be loaded at FE000000 159 160 make distclean 161 make MPC8349ITX_LOWBOOT_config 162 make 163 164 4) Take the u-boot.bin image and flash it at FE000000. 165 166 tftp $loadaddr u-boot.bin 167 protect off FE000000 +$filesize 168 erase FE000000 +$filesize 169 cp.b $loadaddr FE000000 $filesize 170 171 The HRCW in flash is currently set to boot the image at FE000000. 172 173 If you have a hardware debugger, configure it to set the HRCW to 174 B460A000 04040000 if you want to boot the image at FEF00000, or set 175 it to B060A000 04040000 if you want to boot the image at FE000000. 176 177 To change the HRCW in flash to boot the image at FEF00000, use these 178 U-Boot commands: 179 180 cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000 181 mw.b 1020 b4 8 ; modify BMS bit 182 protect off FE000000 +10000 183 erase FE000000 +10000 184 cp.b 1000 FE000000 10000 185 1867. Notes 187 1) The console baudrate for MPC8349EITX is 115200bps. 188