1 /* 2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/mmu.h> 8 #include <asm/io.h> 9 #include <common.h> 10 #include <mpc83xx.h> 11 #include <pci.h> 12 #include <i2c.h> 13 #include <asm/fsl_i2c.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 static struct pci_region pci1_regions[] = { 18 { 19 bus_start: CONFIG_SYS_PCI1_MEM_BASE, 20 phys_start: CONFIG_SYS_PCI1_MEM_PHYS, 21 size: CONFIG_SYS_PCI1_MEM_SIZE, 22 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 23 }, 24 { 25 bus_start: CONFIG_SYS_PCI1_IO_BASE, 26 phys_start: CONFIG_SYS_PCI1_IO_PHYS, 27 size: CONFIG_SYS_PCI1_IO_SIZE, 28 flags: PCI_REGION_IO 29 }, 30 { 31 bus_start: CONFIG_SYS_PCI1_MMIO_BASE, 32 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, 33 size: CONFIG_SYS_PCI1_MMIO_SIZE, 34 flags: PCI_REGION_MEM 35 }, 36 }; 37 38 #ifdef CONFIG_MPC83XX_PCI2 39 static struct pci_region pci2_regions[] = { 40 { 41 bus_start: CONFIG_SYS_PCI2_MEM_BASE, 42 phys_start: CONFIG_SYS_PCI2_MEM_PHYS, 43 size: CONFIG_SYS_PCI2_MEM_SIZE, 44 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 45 }, 46 { 47 bus_start: CONFIG_SYS_PCI2_IO_BASE, 48 phys_start: CONFIG_SYS_PCI2_IO_PHYS, 49 size: CONFIG_SYS_PCI2_IO_SIZE, 50 flags: PCI_REGION_IO 51 }, 52 { 53 bus_start: CONFIG_SYS_PCI2_MMIO_BASE, 54 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, 55 size: CONFIG_SYS_PCI2_MMIO_SIZE, 56 flags: PCI_REGION_MEM 57 }, 58 }; 59 #endif 60 61 #ifndef CONFIG_PCISLAVE 62 void pib_init(void) 63 { 64 u8 val8, orig_i2c_bus; 65 /* 66 * Assign PIB PMC slot to desired PCI bus 67 */ 68 /* Switch temporarily to I2C bus #2 */ 69 orig_i2c_bus = i2c_get_bus_num(); 70 i2c_set_bus_num(1); 71 72 val8 = 0; 73 i2c_write(0x23, 0x6, 1, &val8, 1); 74 i2c_write(0x23, 0x7, 1, &val8, 1); 75 val8 = 0xff; 76 i2c_write(0x23, 0x2, 1, &val8, 1); 77 i2c_write(0x23, 0x3, 1, &val8, 1); 78 79 val8 = 0; 80 i2c_write(0x26, 0x6, 1, &val8, 1); 81 val8 = 0x34; 82 i2c_write(0x26, 0x7, 1, &val8, 1); 83 #if defined(PCI_64BIT) 84 val8 = 0xf4; /* PMC2:PCI1/64-bit */ 85 #elif defined(PCI_ALL_PCI1) 86 val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ 87 #elif defined(PCI_ONE_PCI1) 88 val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ 89 #else 90 val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ 91 #endif 92 i2c_write(0x26, 0x2, 1, &val8, 1); 93 val8 = 0xff; 94 i2c_write(0x26, 0x3, 1, &val8, 1); 95 val8 = 0; 96 i2c_write(0x27, 0x6, 1, &val8, 1); 97 i2c_write(0x27, 0x7, 1, &val8, 1); 98 val8 = 0xff; 99 i2c_write(0x27, 0x2, 1, &val8, 1); 100 val8 = 0xef; 101 i2c_write(0x27, 0x3, 1, &val8, 1); 102 asm("eieio"); 103 104 #if defined(PCI_64BIT) 105 printf("PCI1: 64-bit on PMC2\n"); 106 #elif defined(PCI_ALL_PCI1) 107 printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); 108 #elif defined(PCI_ONE_PCI1) 109 printf("PCI1: 32-bit on PMC1\n"); 110 printf("PCI2: 32-bit on PMC2, PMC3\n"); 111 #else 112 printf("PCI1: 32-bit on PMC1, PMC2\n"); 113 printf("PCI2: 32-bit on PMC3\n"); 114 #endif 115 /* Reset to original I2C bus */ 116 i2c_set_bus_num(orig_i2c_bus); 117 } 118 119 void pci_init_board(void) 120 { 121 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 122 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 123 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 124 #ifndef CONFIG_MPC83XX_PCI2 125 struct pci_region *reg[] = { pci1_regions }; 126 #else 127 struct pci_region *reg[] = { pci1_regions, pci2_regions }; 128 #endif 129 130 /* initialize the PCA9555PW IO expander on the PIB board */ 131 pib_init(); 132 133 /* Enable all 8 PCI_CLK_OUTPUTS */ 134 clk->occr = 0xff000000; 135 udelay(2000); 136 137 /* Configure PCI Local Access Windows */ 138 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 139 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; 140 141 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 142 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; 143 144 udelay(2000); 145 146 #ifndef CONFIG_MPC83XX_PCI2 147 mpc83xx_pci_init(1, reg); 148 #else 149 mpc83xx_pci_init(2, reg); 150 #endif 151 } 152 153 #else 154 void pci_init_board(void) 155 { 156 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 157 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 158 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; 159 struct pci_region *reg[] = { pci1_regions }; 160 161 /* Configure PCI Local Access Windows */ 162 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 163 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; 164 165 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 166 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; 167 168 mpc83xx_pci_init(1, reg); 169 170 /* Configure PCI Inbound Translation Windows (3 1MB windows) */ 171 pci_ctrl->pitar0 = 0x0; 172 pci_ctrl->pibar0 = 0x0; 173 pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | 174 PIWAR_WTT_SNOOP | PIWAR_IWS_1M; 175 176 pci_ctrl->pitar1 = 0x0; 177 pci_ctrl->pibar1 = 0x0; 178 pci_ctrl->piebar1 = 0x0; 179 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | 180 PIWAR_WTT_SNOOP | PIWAR_IWS_1M; 181 182 pci_ctrl->pitar2 = 0x0; 183 pci_ctrl->pibar2 = 0x0; 184 pci_ctrl->piebar2 = 0x0; 185 pci_ctrl->piwar2 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | 186 PIWAR_WTT_SNOOP | PIWAR_IWS_1M; 187 188 /* Unlock the configuration bit */ 189 mpc83xx_pcislave_unlock(0); 190 printf("PCI: Agent mode enabled\n"); 191 } 192 #endif /* CONFIG_PCISLAVE */ 193