1 /* 2 * See file CREDITS for list of people who contributed to this 3 * project. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 * 20 */ 21 22 #include <asm/mmu.h> 23 #include <common.h> 24 #include <asm/global_data.h> 25 #include <pci.h> 26 #include <asm/mpc8349_pci.h> 27 #include <i2c.h> 28 #if defined(CONFIG_OF_LIBFDT) 29 #include <libfdt.h> 30 #include <fdt_support.h> 31 #endif 32 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #ifdef CONFIG_PCI 37 38 /* System RAM mapped to PCI space */ 39 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE 40 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE 41 42 #ifndef CONFIG_PCI_PNP 43 static struct pci_config_table pci_mpc8349emds_config_table[] = { 44 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 45 PCI_IDSEL_NUMBER, PCI_ANY_ID, 46 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 47 PCI_ENET0_MEMADDR, 48 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 49 } 50 }, 51 {} 52 }; 53 #endif 54 55 static struct pci_controller pci_hose[] = { 56 { 57 #ifndef CONFIG_PCI_PNP 58 config_table:pci_mpc8349emds_config_table, 59 #endif 60 }, 61 { 62 #ifndef CONFIG_PCI_PNP 63 config_table:pci_mpc8349emds_config_table, 64 #endif 65 } 66 }; 67 68 /************************************************************************** 69 * 70 * pib_init() -- initialize the PCA9555PW IO expander on the PIB board 71 * 72 */ 73 void 74 pib_init(void) 75 { 76 u8 val8, orig_i2c_bus; 77 /* 78 * Assign PIB PMC slot to desired PCI bus 79 */ 80 /* Switch temporarily to I2C bus #2 */ 81 orig_i2c_bus = i2c_get_bus_num(); 82 i2c_set_bus_num(1); 83 84 val8 = 0; 85 i2c_write(0x23, 0x6, 1, &val8, 1); 86 i2c_write(0x23, 0x7, 1, &val8, 1); 87 val8 = 0xff; 88 i2c_write(0x23, 0x2, 1, &val8, 1); 89 i2c_write(0x23, 0x3, 1, &val8, 1); 90 91 val8 = 0; 92 i2c_write(0x26, 0x6, 1, &val8, 1); 93 val8 = 0x34; 94 i2c_write(0x26, 0x7, 1, &val8, 1); 95 #if defined(PCI_64BIT) 96 val8 = 0xf4; /* PMC2:PCI1/64-bit */ 97 #elif defined(PCI_ALL_PCI1) 98 val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ 99 #elif defined(PCI_ONE_PCI1) 100 val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ 101 #else 102 val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ 103 #endif 104 i2c_write(0x26, 0x2, 1, &val8, 1); 105 val8 = 0xff; 106 i2c_write(0x26, 0x3, 1, &val8, 1); 107 val8 = 0; 108 i2c_write(0x27, 0x6, 1, &val8, 1); 109 i2c_write(0x27, 0x7, 1, &val8, 1); 110 val8 = 0xff; 111 i2c_write(0x27, 0x2, 1, &val8, 1); 112 val8 = 0xef; 113 i2c_write(0x27, 0x3, 1, &val8, 1); 114 asm("eieio"); 115 116 #if defined(PCI_64BIT) 117 printf("PCI1: 64-bit on PMC2\n"); 118 #elif defined(PCI_ALL_PCI1) 119 printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); 120 #elif defined(PCI_ONE_PCI1) 121 printf("PCI1: 32-bit on PMC1\n"); 122 printf("PCI2: 32-bit on PMC2, PMC3\n"); 123 #else 124 printf("PCI1: 32-bit on PMC1, PMC2\n"); 125 printf("PCI2: 32-bit on PMC3\n"); 126 #endif 127 /* Reset to original I2C bus */ 128 i2c_set_bus_num(orig_i2c_bus); 129 } 130 131 /************************************************************************** 132 * pci_init_board() 133 * 134 * NOTICE: PCI2 is not currently supported 135 * 136 */ 137 void 138 pci_init_board(void) 139 { 140 volatile immap_t * immr; 141 volatile clk83xx_t * clk; 142 volatile law83xx_t * pci_law; 143 volatile pot83xx_t * pci_pot; 144 volatile pcictrl83xx_t * pci_ctrl; 145 volatile pciconf83xx_t * pci_conf; 146 u16 reg16; 147 u32 reg32; 148 u32 dev; 149 struct pci_controller * hose; 150 151 immr = (immap_t *)CFG_IMMR; 152 clk = (clk83xx_t *)&immr->clk; 153 pci_law = immr->sysconf.pcilaw; 154 pci_pot = immr->ios.pot; 155 pci_ctrl = immr->pci_ctrl; 156 pci_conf = immr->pci_conf; 157 158 hose = &pci_hose[0]; 159 160 pib_init(); 161 162 /* 163 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode 164 */ 165 166 reg32 = clk->occr; 167 udelay(2000); 168 clk->occr = 0xff000000; 169 udelay(2000); 170 171 /* 172 * Release PCI RST Output signal 173 */ 174 pci_ctrl[0].gcr = 0; 175 udelay(2000); 176 pci_ctrl[0].gcr = 1; 177 178 #ifdef CONFIG_MPC83XX_PCI2 179 pci_ctrl[1].gcr = 0; 180 udelay(2000); 181 pci_ctrl[1].gcr = 1; 182 #endif 183 184 /* We need to wait at least a 1sec based on PCI specs */ 185 { 186 int i; 187 188 for (i = 0; i < 1000; ++i) 189 udelay (1000); 190 } 191 192 /* 193 * Configure PCI Local Access Windows 194 */ 195 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; 196 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; 197 198 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; 199 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; 200 201 /* 202 * Configure PCI Outbound Translation Windows 203 */ 204 205 /* PCI1 mem space - prefetch */ 206 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; 207 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; 208 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); 209 210 /* PCI1 IO space */ 211 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; 212 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; 213 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); 214 215 /* PCI1 mmio - non-prefetch mem space */ 216 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; 217 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; 218 pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); 219 220 /* 221 * Configure PCI Inbound Translation Windows 222 */ 223 224 /* we need RAM mapped to PCI space for the devices to 225 * access main memory */ 226 pci_ctrl[0].pitar1 = 0x0; 227 pci_ctrl[0].pibar1 = 0x0; 228 pci_ctrl[0].piebar1 = 0x0; 229 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); 230 231 hose->first_busno = 0; 232 hose->last_busno = 0xff; 233 234 /* PCI memory prefetch space */ 235 pci_set_region(hose->regions + 0, 236 CFG_PCI1_MEM_BASE, 237 CFG_PCI1_MEM_PHYS, 238 CFG_PCI1_MEM_SIZE, 239 PCI_REGION_MEM|PCI_REGION_PREFETCH); 240 241 /* PCI memory space */ 242 pci_set_region(hose->regions + 1, 243 CFG_PCI1_MMIO_BASE, 244 CFG_PCI1_MMIO_PHYS, 245 CFG_PCI1_MMIO_SIZE, 246 PCI_REGION_MEM); 247 248 /* PCI IO space */ 249 pci_set_region(hose->regions + 2, 250 CFG_PCI1_IO_BASE, 251 CFG_PCI1_IO_PHYS, 252 CFG_PCI1_IO_SIZE, 253 PCI_REGION_IO); 254 255 /* System memory space */ 256 pci_set_region(hose->regions + 3, 257 CONFIG_PCI_SYS_MEM_BUS, 258 CONFIG_PCI_SYS_MEM_PHYS, 259 gd->ram_size, 260 PCI_REGION_MEM | PCI_REGION_MEMORY); 261 262 hose->region_count = 4; 263 264 pci_setup_indirect(hose, 265 (CFG_IMMR+0x8300), 266 (CFG_IMMR+0x8304)); 267 268 pci_register_hose(hose); 269 270 /* 271 * Write to Command register 272 */ 273 reg16 = 0xff; 274 dev = PCI_BDF(hose->first_busno, 0, 0); 275 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); 276 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 277 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); 278 279 /* 280 * Clear non-reserved bits in status register. 281 */ 282 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); 283 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 284 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 285 286 #ifdef CONFIG_PCI_SCAN_SHOW 287 printf("PCI: Bus Dev VenId DevId Class Int\n"); 288 #endif 289 /* 290 * Hose scan. 291 */ 292 hose->last_busno = pci_hose_scan(hose); 293 294 #ifdef CONFIG_MPC83XX_PCI2 295 hose = &pci_hose[1]; 296 297 /* 298 * Configure PCI Outbound Translation Windows 299 */ 300 301 /* PCI2 mem space - prefetch */ 302 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; 303 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; 304 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); 305 306 /* PCI2 IO space */ 307 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; 308 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; 309 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); 310 311 /* PCI2 mmio - non-prefetch mem space */ 312 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; 313 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; 314 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); 315 316 /* 317 * Configure PCI Inbound Translation Windows 318 */ 319 320 /* we need RAM mapped to PCI space for the devices to 321 * access main memory */ 322 pci_ctrl[1].pitar1 = 0x0; 323 pci_ctrl[1].pibar1 = 0x0; 324 pci_ctrl[1].piebar1 = 0x0; 325 pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); 326 327 hose->first_busno = pci_hose[0].last_busno + 1; 328 hose->last_busno = 0xff; 329 330 /* PCI memory prefetch space */ 331 pci_set_region(hose->regions + 0, 332 CFG_PCI2_MEM_BASE, 333 CFG_PCI2_MEM_PHYS, 334 CFG_PCI2_MEM_SIZE, 335 PCI_REGION_MEM|PCI_REGION_PREFETCH); 336 337 /* PCI memory space */ 338 pci_set_region(hose->regions + 1, 339 CFG_PCI2_MMIO_BASE, 340 CFG_PCI2_MMIO_PHYS, 341 CFG_PCI2_MMIO_SIZE, 342 PCI_REGION_MEM); 343 344 /* PCI IO space */ 345 pci_set_region(hose->regions + 2, 346 CFG_PCI2_IO_BASE, 347 CFG_PCI2_IO_PHYS, 348 CFG_PCI2_IO_SIZE, 349 PCI_REGION_IO); 350 351 /* System memory space */ 352 pci_set_region(hose->regions + 3, 353 CONFIG_PCI_SYS_MEM_BUS, 354 CONFIG_PCI_SYS_MEM_PHYS, 355 gd->ram_size, 356 PCI_REGION_MEM | PCI_REGION_MEMORY); 357 358 hose->region_count = 4; 359 360 pci_setup_indirect(hose, 361 (CFG_IMMR+0x8380), 362 (CFG_IMMR+0x8384)); 363 364 pci_register_hose(hose); 365 366 /* 367 * Write to Command register 368 */ 369 reg16 = 0xff; 370 dev = PCI_BDF(hose->first_busno, 0, 0); 371 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); 372 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 373 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); 374 375 /* 376 * Clear non-reserved bits in status register. 377 */ 378 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); 379 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 380 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 381 382 /* 383 * Hose scan. 384 */ 385 hose->last_busno = pci_hose_scan(hose); 386 #endif 387 388 } 389 390 #if defined(CONFIG_OF_LIBFDT) 391 void ft_pci_setup(void *blob, bd_t *bd) 392 { 393 int nodeoffset; 394 int tmp[2]; 395 const char *path; 396 397 nodeoffset = fdt_path_offset(blob, "/aliases"); 398 if (nodeoffset >= 0) { 399 path = fdt_getprop(blob, nodeoffset, "pci0", NULL); 400 if (path) { 401 tmp[0] = cpu_to_be32(pci_hose[0].first_busno); 402 tmp[1] = cpu_to_be32(pci_hose[0].last_busno); 403 do_fixup_by_path(blob, path, "bus-range", 404 &tmp, sizeof(tmp), 1); 405 406 tmp[0] = cpu_to_be32(gd->pci_clk); 407 do_fixup_by_path(blob, path, "clock-frequency", 408 &tmp, sizeof(tmp[0]), 1); 409 } 410 #ifdef CONFIG_MPC83XX_PCI2 411 path = fdt_getprop(blob, nodeoffset, "pci1", NULL); 412 if (path) { 413 tmp[0] = cpu_to_be32(pci_hose[0].first_busno); 414 tmp[1] = cpu_to_be32(pci_hose[0].last_busno); 415 do_fixup_by_path(blob, path, "bus-range", 416 &tmp, sizeof(tmp), 1); 417 418 tmp[0] = cpu_to_be32(gd->pci_clk); 419 do_fixup_by_path(blob, path, "clock-frequency", 420 &tmp, sizeof(tmp[0]), 1); 421 } 422 #endif 423 } 424 } 425 #endif /* CONFIG_OF_LIBFDT */ 426 #endif /* CONFIG_PCI */ 427