1 /* 2 * See file CREDITS for list of people who contributed to this 3 * project. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 * 20 */ 21 22 #include <asm/mmu.h> 23 #include <common.h> 24 #include <asm/global_data.h> 25 #include <pci.h> 26 #include <asm/mpc8349_pci.h> 27 #include <i2c.h> 28 #if defined(CONFIG_OF_FLAT_TREE) 29 #include <ft_build.h> 30 #elif defined(CONFIG_OF_LIBFDT) 31 #include <libfdt.h> 32 #endif 33 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifdef CONFIG_PCI 38 39 /* System RAM mapped to PCI space */ 40 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE 41 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE 42 43 #ifndef CONFIG_PCI_PNP 44 static struct pci_config_table pci_mpc8349emds_config_table[] = { 45 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 46 PCI_IDSEL_NUMBER, PCI_ANY_ID, 47 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 48 PCI_ENET0_MEMADDR, 49 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 50 } 51 }, 52 {} 53 }; 54 #endif 55 56 static struct pci_controller pci_hose[] = { 57 { 58 #ifndef CONFIG_PCI_PNP 59 config_table:pci_mpc8349emds_config_table, 60 #endif 61 }, 62 { 63 #ifndef CONFIG_PCI_PNP 64 config_table:pci_mpc8349emds_config_table, 65 #endif 66 } 67 }; 68 69 /************************************************************************** 70 * 71 * pib_init() -- initialize the PCA9555PW IO expander on the PIB board 72 * 73 */ 74 void 75 pib_init(void) 76 { 77 u8 val8, orig_i2c_bus; 78 /* 79 * Assign PIB PMC slot to desired PCI bus 80 */ 81 /* Switch temporarily to I2C bus #2 */ 82 orig_i2c_bus = i2c_get_bus_num(); 83 i2c_set_bus_num(1); 84 85 val8 = 0; 86 i2c_write(0x23, 0x6, 1, &val8, 1); 87 i2c_write(0x23, 0x7, 1, &val8, 1); 88 val8 = 0xff; 89 i2c_write(0x23, 0x2, 1, &val8, 1); 90 i2c_write(0x23, 0x3, 1, &val8, 1); 91 92 val8 = 0; 93 i2c_write(0x26, 0x6, 1, &val8, 1); 94 val8 = 0x34; 95 i2c_write(0x26, 0x7, 1, &val8, 1); 96 #if defined(PCI_64BIT) 97 val8 = 0xf4; /* PMC2:PCI1/64-bit */ 98 #elif defined(PCI_ALL_PCI1) 99 val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ 100 #elif defined(PCI_ONE_PCI1) 101 val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ 102 #else 103 val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ 104 #endif 105 i2c_write(0x26, 0x2, 1, &val8, 1); 106 val8 = 0xff; 107 i2c_write(0x26, 0x3, 1, &val8, 1); 108 val8 = 0; 109 i2c_write(0x27, 0x6, 1, &val8, 1); 110 i2c_write(0x27, 0x7, 1, &val8, 1); 111 val8 = 0xff; 112 i2c_write(0x27, 0x2, 1, &val8, 1); 113 val8 = 0xef; 114 i2c_write(0x27, 0x3, 1, &val8, 1); 115 asm("eieio"); 116 117 #if defined(PCI_64BIT) 118 printf("PCI1: 64-bit on PMC2\n"); 119 #elif defined(PCI_ALL_PCI1) 120 printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); 121 #elif defined(PCI_ONE_PCI1) 122 printf("PCI1: 32-bit on PMC1\n"); 123 printf("PCI2: 32-bit on PMC2, PMC3\n"); 124 #else 125 printf("PCI1: 32-bit on PMC1, PMC2\n"); 126 printf("PCI2: 32-bit on PMC3\n"); 127 #endif 128 /* Reset to original I2C bus */ 129 i2c_set_bus_num(orig_i2c_bus); 130 } 131 132 /************************************************************************** 133 * pci_init_board() 134 * 135 * NOTICE: PCI2 is not currently supported 136 * 137 */ 138 void 139 pci_init_board(void) 140 { 141 volatile immap_t * immr; 142 volatile clk83xx_t * clk; 143 volatile law83xx_t * pci_law; 144 volatile pot83xx_t * pci_pot; 145 volatile pcictrl83xx_t * pci_ctrl; 146 volatile pciconf83xx_t * pci_conf; 147 u16 reg16; 148 u32 reg32; 149 u32 dev; 150 struct pci_controller * hose; 151 152 immr = (immap_t *)CFG_IMMR; 153 clk = (clk83xx_t *)&immr->clk; 154 pci_law = immr->sysconf.pcilaw; 155 pci_pot = immr->ios.pot; 156 pci_ctrl = immr->pci_ctrl; 157 pci_conf = immr->pci_conf; 158 159 hose = &pci_hose[0]; 160 161 pib_init(); 162 163 /* 164 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode 165 */ 166 167 reg32 = clk->occr; 168 udelay(2000); 169 clk->occr = 0xff000000; 170 udelay(2000); 171 172 /* 173 * Release PCI RST Output signal 174 */ 175 pci_ctrl[0].gcr = 0; 176 udelay(2000); 177 pci_ctrl[0].gcr = 1; 178 179 #ifdef CONFIG_MPC83XX_PCI2 180 pci_ctrl[1].gcr = 0; 181 udelay(2000); 182 pci_ctrl[1].gcr = 1; 183 #endif 184 185 /* We need to wait at least a 1sec based on PCI specs */ 186 { 187 int i; 188 189 for (i = 0; i < 1000; ++i) 190 udelay (1000); 191 } 192 193 /* 194 * Configure PCI Local Access Windows 195 */ 196 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; 197 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; 198 199 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; 200 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; 201 202 /* 203 * Configure PCI Outbound Translation Windows 204 */ 205 206 /* PCI1 mem space - prefetch */ 207 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; 208 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; 209 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); 210 211 /* PCI1 IO space */ 212 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; 213 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; 214 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); 215 216 /* PCI1 mmio - non-prefetch mem space */ 217 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; 218 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; 219 pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); 220 221 /* 222 * Configure PCI Inbound Translation Windows 223 */ 224 225 /* we need RAM mapped to PCI space for the devices to 226 * access main memory */ 227 pci_ctrl[0].pitar1 = 0x0; 228 pci_ctrl[0].pibar1 = 0x0; 229 pci_ctrl[0].piebar1 = 0x0; 230 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); 231 232 hose->first_busno = 0; 233 hose->last_busno = 0xff; 234 235 /* PCI memory prefetch space */ 236 pci_set_region(hose->regions + 0, 237 CFG_PCI1_MEM_BASE, 238 CFG_PCI1_MEM_PHYS, 239 CFG_PCI1_MEM_SIZE, 240 PCI_REGION_MEM|PCI_REGION_PREFETCH); 241 242 /* PCI memory space */ 243 pci_set_region(hose->regions + 1, 244 CFG_PCI1_MMIO_BASE, 245 CFG_PCI1_MMIO_PHYS, 246 CFG_PCI1_MMIO_SIZE, 247 PCI_REGION_MEM); 248 249 /* PCI IO space */ 250 pci_set_region(hose->regions + 2, 251 CFG_PCI1_IO_BASE, 252 CFG_PCI1_IO_PHYS, 253 CFG_PCI1_IO_SIZE, 254 PCI_REGION_IO); 255 256 /* System memory space */ 257 pci_set_region(hose->regions + 3, 258 CONFIG_PCI_SYS_MEM_BUS, 259 CONFIG_PCI_SYS_MEM_PHYS, 260 gd->ram_size, 261 PCI_REGION_MEM | PCI_REGION_MEMORY); 262 263 hose->region_count = 4; 264 265 pci_setup_indirect(hose, 266 (CFG_IMMR+0x8300), 267 (CFG_IMMR+0x8304)); 268 269 pci_register_hose(hose); 270 271 /* 272 * Write to Command register 273 */ 274 reg16 = 0xff; 275 dev = PCI_BDF(hose->first_busno, 0, 0); 276 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); 277 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 278 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); 279 280 /* 281 * Clear non-reserved bits in status register. 282 */ 283 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); 284 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 285 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 286 287 #ifdef CONFIG_PCI_SCAN_SHOW 288 printf("PCI: Bus Dev VenId DevId Class Int\n"); 289 #endif 290 /* 291 * Hose scan. 292 */ 293 hose->last_busno = pci_hose_scan(hose); 294 295 #ifdef CONFIG_MPC83XX_PCI2 296 hose = &pci_hose[1]; 297 298 /* 299 * Configure PCI Outbound Translation Windows 300 */ 301 302 /* PCI2 mem space - prefetch */ 303 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; 304 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; 305 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); 306 307 /* PCI2 IO space */ 308 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; 309 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; 310 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); 311 312 /* PCI2 mmio - non-prefetch mem space */ 313 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; 314 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; 315 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); 316 317 /* 318 * Configure PCI Inbound Translation Windows 319 */ 320 321 /* we need RAM mapped to PCI space for the devices to 322 * access main memory */ 323 pci_ctrl[1].pitar1 = 0x0; 324 pci_ctrl[1].pibar1 = 0x0; 325 pci_ctrl[1].piebar1 = 0x0; 326 pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); 327 328 hose->first_busno = pci_hose[0].last_busno + 1; 329 hose->last_busno = 0xff; 330 331 /* PCI memory prefetch space */ 332 pci_set_region(hose->regions + 0, 333 CFG_PCI2_MEM_BASE, 334 CFG_PCI2_MEM_PHYS, 335 CFG_PCI2_MEM_SIZE, 336 PCI_REGION_MEM|PCI_REGION_PREFETCH); 337 338 /* PCI memory space */ 339 pci_set_region(hose->regions + 1, 340 CFG_PCI2_MMIO_BASE, 341 CFG_PCI2_MMIO_PHYS, 342 CFG_PCI2_MMIO_SIZE, 343 PCI_REGION_MEM); 344 345 /* PCI IO space */ 346 pci_set_region(hose->regions + 2, 347 CFG_PCI2_IO_BASE, 348 CFG_PCI2_IO_PHYS, 349 CFG_PCI2_IO_SIZE, 350 PCI_REGION_IO); 351 352 /* System memory space */ 353 pci_set_region(hose->regions + 3, 354 CONFIG_PCI_SYS_MEM_BUS, 355 CONFIG_PCI_SYS_MEM_PHYS, 356 gd->ram_size, 357 PCI_REGION_MEM | PCI_REGION_MEMORY); 358 359 hose->region_count = 4; 360 361 pci_setup_indirect(hose, 362 (CFG_IMMR+0x8380), 363 (CFG_IMMR+0x8384)); 364 365 pci_register_hose(hose); 366 367 /* 368 * Write to Command register 369 */ 370 reg16 = 0xff; 371 dev = PCI_BDF(hose->first_busno, 0, 0); 372 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); 373 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 374 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); 375 376 /* 377 * Clear non-reserved bits in status register. 378 */ 379 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); 380 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 381 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 382 383 /* 384 * Hose scan. 385 */ 386 hose->last_busno = pci_hose_scan(hose); 387 #endif 388 389 } 390 391 #if defined(CONFIG_OF_LIBFDT) 392 void 393 ft_pci_setup(void *blob, bd_t *bd) 394 { 395 int nodeoffset; 396 int err; 397 int tmp[2]; 398 399 nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500"); 400 if (nodeoffset >= 0) { 401 tmp[0] = cpu_to_be32(pci_hose[0].first_busno); 402 tmp[1] = cpu_to_be32(pci_hose[0].last_busno); 403 err = fdt_setprop(blob, nodeoffset, "bus-range", 404 tmp, sizeof(tmp)); 405 406 tmp[0] = cpu_to_be32(gd->pci_clk); 407 err = fdt_setprop(blob, nodeoffset, "clock-frequency", 408 tmp, sizeof(tmp[0])); 409 } 410 #ifdef CONFIG_MPC83XX_PCI2 411 nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8600"); 412 if (nodeoffset >= 0) { 413 tmp[0] = cpu_to_be32(pci_hose[1].first_busno); 414 tmp[1] = cpu_to_be32(pci_hose[1].last_busno); 415 err = fdt_setprop(blob, nodeoffset, "bus-range", 416 tmp, sizeof(tmp)); 417 418 tmp[0] = cpu_to_be32(gd->pci_clk); 419 err = fdt_setprop(blob, nodeoffset, "clock-frequency", 420 tmp, sizeof(tmp[0])); 421 } 422 #endif 423 } 424 #elif defined(CONFIG_OF_FLAT_TREE) 425 void 426 ft_pci_setup(void *blob, bd_t *bd) 427 { 428 u32 *p; 429 int len; 430 431 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); 432 if (p != NULL) { 433 p[0] = pci_hose[0].first_busno; 434 p[1] = pci_hose[0].last_busno; 435 } 436 437 #ifdef CONFIG_MPC83XX_PCI2 438 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); 439 if (p != NULL) { 440 p[0] = pci_hose[1].first_busno; 441 p[1] = pci_hose[1].last_busno; 442 } 443 #endif 444 } 445 #endif /* CONFIG_OF_FLAT_TREE */ 446 #endif /* CONFIG_PCI */ 447