1 /* 2 * (C) Copyright 2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 */ 24 25 #include <common.h> 26 #include <ioports.h> 27 #include <mpc83xx.h> 28 #include <asm/mpc8349_pci.h> 29 #include <i2c.h> 30 #include <spi.h> 31 #include <miiphy.h> 32 #ifdef CONFIG_FSL_DDR2 33 #include <asm/fsl_ddr_sdram.h> 34 #else 35 #include <spd_sdram.h> 36 #endif 37 38 #if defined(CONFIG_OF_LIBFDT) 39 #include <libfdt.h> 40 #endif 41 42 int fixed_sdram(void); 43 void sdram_init(void); 44 45 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx) 46 void ddr_enable_ecc(unsigned int dram_size); 47 #endif 48 49 int board_early_init_f (void) 50 { 51 volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR; 52 53 /* Enable flash write */ 54 bcsr[1] &= ~0x01; 55 56 #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY 57 /* Use USB PHY on SYS board */ 58 bcsr[5] |= 0x02; 59 #endif 60 61 return 0; 62 } 63 64 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) 65 66 phys_size_t initdram (int board_type) 67 { 68 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 69 phys_size_t msize = 0; 70 71 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 72 return -1; 73 74 /* DDR SDRAM - Main SODIMM */ 75 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 76 #if defined(CONFIG_SPD_EEPROM) 77 #ifndef CONFIG_FSL_DDR2 78 msize = spd_sdram() * 1024 * 1024; 79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 80 ddr_enable_ecc(msize); 81 #endif 82 #else 83 msize = fsl_ddr_sdram(); 84 #endif 85 #else 86 msize = fixed_sdram() * 1024 * 1024; 87 #endif 88 /* 89 * Initialize SDRAM if it is on local bus. 90 */ 91 sdram_init(); 92 93 /* return total bus SDRAM size(bytes) -- DDR */ 94 return msize; 95 } 96 97 #if !defined(CONFIG_SPD_EEPROM) 98 /************************************************************************* 99 * fixed sdram init -- doesn't use serial presence detect. 100 ************************************************************************/ 101 int fixed_sdram(void) 102 { 103 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 104 u32 msize = CONFIG_SYS_DDR_SIZE; 105 u32 ddr_size = msize << 20; /* DDR size in bytes */ 106 u32 ddr_size_log2 = __ilog2(ddr_size); 107 108 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 109 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 110 111 #if (CONFIG_SYS_DDR_SIZE != 256) 112 #warning Currenly any ddr size other than 256 is not supported 113 #endif 114 #ifdef CONFIG_DDR_II 115 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS; 116 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; 117 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 118 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 119 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 120 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 121 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; 122 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; 123 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 124 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; 125 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 126 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; 127 #else 128 129 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) 130 #warning Chip select bounds is only configurable in 16MB increments 131 #endif 132 im->ddr.csbnds[2].csbnds = 133 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | 134 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> 135 CSBNDS_EA_SHIFT) & CSBNDS_EA); 136 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; 137 138 /* currently we use only one CS, so disable the other banks */ 139 im->ddr.cs_config[0] = 0; 140 im->ddr.cs_config[1] = 0; 141 im->ddr.cs_config[3] = 0; 142 143 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 144 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 145 146 im->ddr.sdram_cfg = 147 SDRAM_CFG_SREN 148 #if defined(CONFIG_DDR_2T_TIMING) 149 | SDRAM_CFG_2T_EN 150 #endif 151 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; 152 #if defined (CONFIG_DDR_32BIT) 153 /* for 32-bit mode burst length is 8 */ 154 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); 155 #endif 156 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 157 158 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 159 #endif 160 udelay(200); 161 162 /* enable DDR controller */ 163 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 164 return msize; 165 } 166 #endif/*!CONFIG_SYS_SPD_EEPROM*/ 167 168 169 int checkboard (void) 170 { 171 /* 172 * Warning: do not read the BCSR registers here 173 * 174 * There is a timing bug in the 8349E and 8349EA BCSR code 175 * version 1.2 (read from BCSR 11) that will cause the CFI 176 * flash initialization code to overwrite BCSR 0, disabling 177 * the serial ports and gigabit ethernet 178 */ 179 180 puts("Board: Freescale MPC8349EMDS\n"); 181 return 0; 182 } 183 184 /* 185 * if MPC8349EMDS is soldered with SDRAM 186 */ 187 #if defined(CONFIG_SYS_BR2_PRELIM) \ 188 && defined(CONFIG_SYS_OR2_PRELIM) \ 189 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ 190 && defined(CONFIG_SYS_LBLAWAR2_PRELIM) 191 /* 192 * Initialize SDRAM memory on the Local Bus. 193 */ 194 195 void sdram_init(void) 196 { 197 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 198 volatile fsl_lbc_t *lbc = &immap->im_lbc; 199 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 200 201 /* 202 * Setup SDRAM Base and Option Registers, already done in cpu_init.c 203 */ 204 205 /* setup mtrpt, lsrt and lbcr for LB bus */ 206 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 207 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 208 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 209 asm("sync"); 210 211 /* 212 * Configure the SDRAM controller Machine Mode Register. 213 */ 214 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ 215 216 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ 217 asm("sync"); 218 *sdram_addr = 0xff; 219 udelay(100); 220 221 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ 222 asm("sync"); 223 /*1 times*/ 224 *sdram_addr = 0xff; 225 udelay(100); 226 /*2 times*/ 227 *sdram_addr = 0xff; 228 udelay(100); 229 /*3 times*/ 230 *sdram_addr = 0xff; 231 udelay(100); 232 /*4 times*/ 233 *sdram_addr = 0xff; 234 udelay(100); 235 /*5 times*/ 236 *sdram_addr = 0xff; 237 udelay(100); 238 /*6 times*/ 239 *sdram_addr = 0xff; 240 udelay(100); 241 /*7 times*/ 242 *sdram_addr = 0xff; 243 udelay(100); 244 /*8 times*/ 245 *sdram_addr = 0xff; 246 udelay(100); 247 248 /* 0x58636733; mode register write operation */ 249 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; 250 asm("sync"); 251 *sdram_addr = 0xff; 252 udelay(100); 253 254 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ 255 asm("sync"); 256 *sdram_addr = 0xff; 257 udelay(100); 258 } 259 #else 260 void sdram_init(void) 261 { 262 } 263 #endif 264 265 /* 266 * The following are used to control the SPI chip selects for the SPI command. 267 */ 268 #ifdef CONFIG_MPC8XXX_SPI 269 270 #define SPI_CS_MASK 0x80000000 271 272 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 273 { 274 return bus == 0 && cs == 0; 275 } 276 277 void spi_cs_activate(struct spi_slave *slave) 278 { 279 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; 280 281 iopd->dat &= ~SPI_CS_MASK; 282 } 283 284 void spi_cs_deactivate(struct spi_slave *slave) 285 { 286 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; 287 288 iopd->dat |= SPI_CS_MASK; 289 } 290 #endif /* CONFIG_HARD_SPI */ 291 292 #if defined(CONFIG_OF_BOARD_SETUP) 293 void ft_board_setup(void *blob, bd_t *bd) 294 { 295 ft_cpu_setup(blob, bd); 296 #ifdef CONFIG_PCI 297 ft_pci_setup(blob, bd); 298 #endif 299 } 300 #endif 301