1 /* 2 * (C) Copyright 2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 */ 24 25 #include <common.h> 26 #include <ioports.h> 27 #include <mpc83xx.h> 28 #include <asm/mpc8349_pci.h> 29 #include <i2c.h> 30 #include <spi.h> 31 #include <miiphy.h> 32 #ifdef CONFIG_FSL_DDR2 33 #include <asm/fsl_ddr_sdram.h> 34 #else 35 #include <spd_sdram.h> 36 #endif 37 38 #if defined(CONFIG_OF_LIBFDT) 39 #include <libfdt.h> 40 #endif 41 42 int fixed_sdram(void); 43 void sdram_init(void); 44 45 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx) 46 void ddr_enable_ecc(unsigned int dram_size); 47 #endif 48 49 int board_early_init_f (void) 50 { 51 volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR; 52 53 /* Enable flash write */ 54 bcsr[1] &= ~0x01; 55 56 #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY 57 /* Use USB PHY on SYS board */ 58 bcsr[5] |= 0x02; 59 #endif 60 61 return 0; 62 } 63 64 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) 65 66 phys_size_t initdram (int board_type) 67 { 68 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 69 phys_size_t msize = 0; 70 71 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 72 return -1; 73 74 /* DDR SDRAM - Main SODIMM */ 75 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 76 #if defined(CONFIG_SPD_EEPROM) 77 #ifndef CONFIG_FSL_DDR2 78 msize = spd_sdram() * 1024 * 1024; 79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 80 ddr_enable_ecc(msize); 81 #endif 82 #else 83 msize = fsl_ddr_sdram(); 84 #endif 85 #else 86 msize = fixed_sdram() * 1024 * 1024; 87 #endif 88 /* 89 * Initialize SDRAM if it is on local bus. 90 */ 91 sdram_init(); 92 93 /* return total bus SDRAM size(bytes) -- DDR */ 94 return msize; 95 } 96 97 #if !defined(CONFIG_SPD_EEPROM) 98 /************************************************************************* 99 * fixed sdram init -- doesn't use serial presence detect. 100 ************************************************************************/ 101 int fixed_sdram(void) 102 { 103 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 104 u32 msize = 0; 105 u32 ddr_size; 106 u32 ddr_size_log2; 107 108 msize = CONFIG_SYS_DDR_SIZE; 109 for (ddr_size = msize << 20, ddr_size_log2 = 0; 110 (ddr_size > 1); 111 ddr_size = ddr_size>>1, ddr_size_log2++) { 112 if (ddr_size & 1) { 113 return -1; 114 } 115 } 116 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 117 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 118 119 #if (CONFIG_SYS_DDR_SIZE != 256) 120 #warning Currenly any ddr size other than 256 is not supported 121 #endif 122 #ifdef CONFIG_DDR_II 123 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS; 124 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; 125 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 126 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 127 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 128 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 129 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; 130 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; 131 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 132 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; 133 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 134 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; 135 #else 136 im->ddr.csbnds[2].csbnds = 0x0000000f; 137 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG; 138 139 /* currently we use only one CS, so disable the other banks */ 140 im->ddr.cs_config[0] = 0; 141 im->ddr.cs_config[1] = 0; 142 im->ddr.cs_config[3] = 0; 143 144 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 145 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 146 147 im->ddr.sdram_cfg = 148 SDRAM_CFG_SREN 149 #if defined(CONFIG_DDR_2T_TIMING) 150 | SDRAM_CFG_2T_EN 151 #endif 152 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; 153 #if defined (CONFIG_DDR_32BIT) 154 /* for 32-bit mode burst length is 8 */ 155 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); 156 #endif 157 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 158 159 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 160 #endif 161 udelay(200); 162 163 /* enable DDR controller */ 164 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 165 return msize; 166 } 167 #endif/*!CONFIG_SYS_SPD_EEPROM*/ 168 169 170 int checkboard (void) 171 { 172 /* 173 * Warning: do not read the BCSR registers here 174 * 175 * There is a timing bug in the 8349E and 8349EA BCSR code 176 * version 1.2 (read from BCSR 11) that will cause the CFI 177 * flash initialization code to overwrite BCSR 0, disabling 178 * the serial ports and gigabit ethernet 179 */ 180 181 puts("Board: Freescale MPC8349EMDS\n"); 182 return 0; 183 } 184 185 /* 186 * if MPC8349EMDS is soldered with SDRAM 187 */ 188 #if defined(CONFIG_SYS_BR2_PRELIM) \ 189 && defined(CONFIG_SYS_OR2_PRELIM) \ 190 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ 191 && defined(CONFIG_SYS_LBLAWAR2_PRELIM) 192 /* 193 * Initialize SDRAM memory on the Local Bus. 194 */ 195 196 void sdram_init(void) 197 { 198 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 199 volatile fsl_lbc_t *lbc = &immap->im_lbc; 200 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 201 202 /* 203 * Setup SDRAM Base and Option Registers, already done in cpu_init.c 204 */ 205 206 /* setup mtrpt, lsrt and lbcr for LB bus */ 207 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 208 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 209 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 210 asm("sync"); 211 212 /* 213 * Configure the SDRAM controller Machine Mode Register. 214 */ 215 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ 216 217 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ 218 asm("sync"); 219 *sdram_addr = 0xff; 220 udelay(100); 221 222 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ 223 asm("sync"); 224 /*1 times*/ 225 *sdram_addr = 0xff; 226 udelay(100); 227 /*2 times*/ 228 *sdram_addr = 0xff; 229 udelay(100); 230 /*3 times*/ 231 *sdram_addr = 0xff; 232 udelay(100); 233 /*4 times*/ 234 *sdram_addr = 0xff; 235 udelay(100); 236 /*5 times*/ 237 *sdram_addr = 0xff; 238 udelay(100); 239 /*6 times*/ 240 *sdram_addr = 0xff; 241 udelay(100); 242 /*7 times*/ 243 *sdram_addr = 0xff; 244 udelay(100); 245 /*8 times*/ 246 *sdram_addr = 0xff; 247 udelay(100); 248 249 /* 0x58636733; mode register write operation */ 250 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; 251 asm("sync"); 252 *sdram_addr = 0xff; 253 udelay(100); 254 255 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ 256 asm("sync"); 257 *sdram_addr = 0xff; 258 udelay(100); 259 } 260 #else 261 void sdram_init(void) 262 { 263 } 264 #endif 265 266 /* 267 * The following are used to control the SPI chip selects for the SPI command. 268 */ 269 #ifdef CONFIG_MPC8XXX_SPI 270 271 #define SPI_CS_MASK 0x80000000 272 273 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 274 { 275 return bus == 0 && cs == 0; 276 } 277 278 void spi_cs_activate(struct spi_slave *slave) 279 { 280 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; 281 282 iopd->dat &= ~SPI_CS_MASK; 283 } 284 285 void spi_cs_deactivate(struct spi_slave *slave) 286 { 287 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; 288 289 iopd->dat |= SPI_CS_MASK; 290 } 291 #endif /* CONFIG_HARD_SPI */ 292 293 #if defined(CONFIG_OF_BOARD_SETUP) 294 void ft_board_setup(void *blob, bd_t *bd) 295 { 296 ft_cpu_setup(blob, bd); 297 #ifdef CONFIG_PCI 298 ft_pci_setup(blob, bd); 299 #endif 300 } 301 #endif 302