1 /* 2 * (C) Copyright 2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 */ 24 25 #include <common.h> 26 #include <ioports.h> 27 #include <mpc83xx.h> 28 #include <asm/mpc8349_pci.h> 29 #include <i2c.h> 30 #include <spd.h> 31 #include <miiphy.h> 32 #if defined(CONFIG_SPD_EEPROM) 33 #include <spd_sdram.h> 34 #endif 35 #if defined(CONFIG_OF_LIBFDT) 36 #include <libfdt.h> 37 #endif 38 39 int fixed_sdram(void); 40 void sdram_init(void); 41 42 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) 43 void ddr_enable_ecc(unsigned int dram_size); 44 #endif 45 46 int board_early_init_f (void) 47 { 48 volatile u8* bcsr = (volatile u8*)CFG_BCSR; 49 50 /* Enable flash write */ 51 bcsr[1] &= ~0x01; 52 53 #ifdef CFG_USE_MPC834XSYS_USB_PHY 54 /* Use USB PHY on SYS board */ 55 bcsr[5] |= 0x02; 56 #endif 57 58 return 0; 59 } 60 61 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) 62 63 long int initdram (int board_type) 64 { 65 volatile immap_t *im = (immap_t *)CFG_IMMR; 66 u32 msize = 0; 67 68 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 69 return -1; 70 71 /* DDR SDRAM - Main SODIMM */ 72 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; 73 #if defined(CONFIG_SPD_EEPROM) 74 msize = spd_sdram(); 75 #else 76 msize = fixed_sdram(); 77 #endif 78 /* 79 * Initialize SDRAM if it is on local bus. 80 */ 81 sdram_init(); 82 83 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 84 /* 85 * Initialize and enable DDR ECC. 86 */ 87 ddr_enable_ecc(msize * 1024 * 1024); 88 #endif 89 90 /* return total bus SDRAM size(bytes) -- DDR */ 91 return (msize * 1024 * 1024); 92 } 93 94 #if !defined(CONFIG_SPD_EEPROM) 95 /************************************************************************* 96 * fixed sdram init -- doesn't use serial presence detect. 97 ************************************************************************/ 98 int fixed_sdram(void) 99 { 100 volatile immap_t *im = (immap_t *)CFG_IMMR; 101 u32 msize = 0; 102 u32 ddr_size; 103 u32 ddr_size_log2; 104 105 msize = CFG_DDR_SIZE; 106 for (ddr_size = msize << 20, ddr_size_log2 = 0; 107 (ddr_size > 1); 108 ddr_size = ddr_size>>1, ddr_size_log2++) { 109 if (ddr_size & 1) { 110 return -1; 111 } 112 } 113 im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); 114 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 115 116 #if (CFG_DDR_SIZE != 256) 117 #warning Currenly any ddr size other than 256 is not supported 118 #endif 119 #ifdef CONFIG_DDR_II 120 im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS; 121 im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG; 122 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 123 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 124 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 125 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 126 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 127 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 128 im->ddr.sdram_mode = CFG_DDR_MODE; 129 im->ddr.sdram_mode2 = CFG_DDR_MODE2; 130 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 131 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; 132 #else 133 im->ddr.csbnds[2].csbnds = 0x0000000f; 134 im->ddr.cs_config[2] = CFG_DDR_CONFIG; 135 136 /* currently we use only one CS, so disable the other banks */ 137 im->ddr.cs_config[0] = 0; 138 im->ddr.cs_config[1] = 0; 139 im->ddr.cs_config[3] = 0; 140 141 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 142 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 143 144 im->ddr.sdram_cfg = 145 SDRAM_CFG_SREN 146 #if defined(CONFIG_DDR_2T_TIMING) 147 | SDRAM_CFG_2T_EN 148 #endif 149 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; 150 #if defined (CONFIG_DDR_32BIT) 151 /* for 32-bit mode burst length is 8 */ 152 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); 153 #endif 154 im->ddr.sdram_mode = CFG_DDR_MODE; 155 156 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 157 #endif 158 udelay(200); 159 160 /* enable DDR controller */ 161 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 162 return msize; 163 } 164 #endif/*!CFG_SPD_EEPROM*/ 165 166 167 int checkboard (void) 168 { 169 puts("Board: Freescale MPC8349EMDS\n"); 170 return 0; 171 } 172 173 /* 174 * if MPC8349EMDS is soldered with SDRAM 175 */ 176 #if defined(CFG_BR2_PRELIM) \ 177 && defined(CFG_OR2_PRELIM) \ 178 && defined(CFG_LBLAWBAR2_PRELIM) \ 179 && defined(CFG_LBLAWAR2_PRELIM) 180 /* 181 * Initialize SDRAM memory on the Local Bus. 182 */ 183 184 void sdram_init(void) 185 { 186 volatile immap_t *immap = (immap_t *)CFG_IMMR; 187 volatile lbus83xx_t *lbc= &immap->lbus; 188 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 189 190 /* 191 * Setup SDRAM Base and Option Registers, already done in cpu_init.c 192 */ 193 194 /* setup mtrpt, lsrt and lbcr for LB bus */ 195 lbc->lbcr = CFG_LBC_LBCR; 196 lbc->mrtpr = CFG_LBC_MRTPR; 197 lbc->lsrt = CFG_LBC_LSRT; 198 asm("sync"); 199 200 /* 201 * Configure the SDRAM controller Machine Mode Register. 202 */ 203 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ 204 205 lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ 206 asm("sync"); 207 *sdram_addr = 0xff; 208 udelay(100); 209 210 lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ 211 asm("sync"); 212 /*1 times*/ 213 *sdram_addr = 0xff; 214 udelay(100); 215 /*2 times*/ 216 *sdram_addr = 0xff; 217 udelay(100); 218 /*3 times*/ 219 *sdram_addr = 0xff; 220 udelay(100); 221 /*4 times*/ 222 *sdram_addr = 0xff; 223 udelay(100); 224 /*5 times*/ 225 *sdram_addr = 0xff; 226 udelay(100); 227 /*6 times*/ 228 *sdram_addr = 0xff; 229 udelay(100); 230 /*7 times*/ 231 *sdram_addr = 0xff; 232 udelay(100); 233 /*8 times*/ 234 *sdram_addr = 0xff; 235 udelay(100); 236 237 /* 0x58636733; mode register write operation */ 238 lbc->lsdmr = CFG_LBC_LSDMR_4; 239 asm("sync"); 240 *sdram_addr = 0xff; 241 udelay(100); 242 243 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ 244 asm("sync"); 245 *sdram_addr = 0xff; 246 udelay(100); 247 } 248 #else 249 void sdram_init(void) 250 { 251 } 252 #endif 253 254 #if defined(CONFIG_OF_BOARD_SETUP) 255 void ft_board_setup(void *blob, bd_t *bd) 256 { 257 ft_cpu_setup(blob, bd); 258 #ifdef CONFIG_PCI 259 ft_pci_setup(blob, bd); 260 #endif 261 } 262 #endif 263