1 /*
2  * (C) Copyright 2006
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <ioports.h>
10 #include <mpc83xx.h>
11 #include <asm/mpc8349_pci.h>
12 #include <i2c.h>
13 #include <spi.h>
14 #include <miiphy.h>
15 #ifdef CONFIG_SYS_FSL_DDR2
16 #include <fsl_ddr_sdram.h>
17 #else
18 #include <spd_sdram.h>
19 #endif
20 
21 #if defined(CONFIG_OF_LIBFDT)
22 #include <libfdt.h>
23 #endif
24 
25 int fixed_sdram(void);
26 void sdram_init(void);
27 
28 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
29 void ddr_enable_ecc(unsigned int dram_size);
30 #endif
31 
32 int board_early_init_f (void)
33 {
34 	volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
35 
36 	/* Enable flash write */
37 	bcsr[1] &= ~0x01;
38 
39 #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
40 	/* Use USB PHY on SYS board */
41 	bcsr[5] |= 0x02;
42 #endif
43 
44 	return 0;
45 }
46 
47 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
48 
49 phys_size_t initdram (int board_type)
50 {
51 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
52 	phys_size_t msize = 0;
53 
54 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
55 		return -1;
56 
57 	/* DDR SDRAM - Main SODIMM */
58 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
59 #if defined(CONFIG_SPD_EEPROM)
60 #ifndef CONFIG_SYS_FSL_DDR2
61 	msize = spd_sdram() * 1024 * 1024;
62 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
63 	ddr_enable_ecc(msize);
64 #endif
65 #else
66 	msize = fsl_ddr_sdram();
67 #endif
68 #else
69 	msize = fixed_sdram() * 1024 * 1024;
70 #endif
71 	/*
72 	 * Initialize SDRAM if it is on local bus.
73 	 */
74 	sdram_init();
75 
76 	/* return total bus SDRAM size(bytes)  -- DDR */
77 	return msize;
78 }
79 
80 #if !defined(CONFIG_SPD_EEPROM)
81 /*************************************************************************
82  *  fixed sdram init -- doesn't use serial presence detect.
83  ************************************************************************/
84 int fixed_sdram(void)
85 {
86 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
87 	u32 msize = CONFIG_SYS_DDR_SIZE;
88 	u32 ddr_size = msize << 20;	/* DDR size in bytes */
89 	u32 ddr_size_log2 = __ilog2(ddr_size);
90 
91 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
92 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
93 
94 #if (CONFIG_SYS_DDR_SIZE != 256)
95 #warning Currenly any ddr size other than 256 is not supported
96 #endif
97 #ifdef CONFIG_DDR_II
98 	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
99 	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
100 	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
101 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
102 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
103 	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
104 	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
105 	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
106 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
107 	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
108 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
109 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
110 #else
111 
112 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
113 #warning Chip select bounds is only configurable in 16MB increments
114 #endif
115 	im->ddr.csbnds[2].csbnds =
116 		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
117 		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
118 				CSBNDS_EA_SHIFT) & CSBNDS_EA);
119 	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
120 
121 	/* currently we use only one CS, so disable the other banks */
122 	im->ddr.cs_config[0] = 0;
123 	im->ddr.cs_config[1] = 0;
124 	im->ddr.cs_config[3] = 0;
125 
126 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
127 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
128 
129 	im->ddr.sdram_cfg =
130 		SDRAM_CFG_SREN
131 #if defined(CONFIG_DDR_2T_TIMING)
132 		| SDRAM_CFG_2T_EN
133 #endif
134 		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
135 #if defined (CONFIG_DDR_32BIT)
136 	/* for 32-bit mode burst length is 8 */
137 	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
138 #endif
139 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
140 
141 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
142 #endif
143 	udelay(200);
144 
145 	/* enable DDR controller */
146 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
147 	return msize;
148 }
149 #endif/*!CONFIG_SYS_SPD_EEPROM*/
150 
151 
152 int checkboard (void)
153 {
154 	/*
155 	 * Warning: do not read the BCSR registers here
156 	 *
157 	 * There is a timing bug in the 8349E and 8349EA BCSR code
158 	 * version 1.2 (read from BCSR 11) that will cause the CFI
159 	 * flash initialization code to overwrite BCSR 0, disabling
160 	 * the serial ports and gigabit ethernet
161 	 */
162 
163 	puts("Board: Freescale MPC8349EMDS\n");
164 	return 0;
165 }
166 
167 /*
168  * if MPC8349EMDS is soldered with SDRAM
169  */
170 #if defined(CONFIG_SYS_BR2_PRELIM)  \
171 	&& defined(CONFIG_SYS_OR2_PRELIM) \
172 	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
173 	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
174 /*
175  * Initialize SDRAM memory on the Local Bus.
176  */
177 
178 void sdram_init(void)
179 {
180 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
181 	volatile fsl_lbc_t *lbc = &immap->im_lbc;
182 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
183 
184 	/*
185 	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
186 	 */
187 
188 	/* setup mtrpt, lsrt and lbcr for LB bus */
189 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
190 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
191 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
192 	asm("sync");
193 
194 	/*
195 	 * Configure the SDRAM controller Machine Mode Register.
196 	 */
197 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
198 
199 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
200 	asm("sync");
201 	*sdram_addr = 0xff;
202 	udelay(100);
203 
204 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
205 	asm("sync");
206 	/*1 times*/
207 	*sdram_addr = 0xff;
208 	udelay(100);
209 	/*2 times*/
210 	*sdram_addr = 0xff;
211 	udelay(100);
212 	/*3 times*/
213 	*sdram_addr = 0xff;
214 	udelay(100);
215 	/*4 times*/
216 	*sdram_addr = 0xff;
217 	udelay(100);
218 	/*5 times*/
219 	*sdram_addr = 0xff;
220 	udelay(100);
221 	/*6 times*/
222 	*sdram_addr = 0xff;
223 	udelay(100);
224 	/*7 times*/
225 	*sdram_addr = 0xff;
226 	udelay(100);
227 	/*8 times*/
228 	*sdram_addr = 0xff;
229 	udelay(100);
230 
231 	/* 0x58636733; mode register write operation */
232 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
233 	asm("sync");
234 	*sdram_addr = 0xff;
235 	udelay(100);
236 
237 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
238 	asm("sync");
239 	*sdram_addr = 0xff;
240 	udelay(100);
241 }
242 #else
243 void sdram_init(void)
244 {
245 }
246 #endif
247 
248 /*
249  * The following are used to control the SPI chip selects for the SPI command.
250  */
251 #ifdef CONFIG_MPC8XXX_SPI
252 
253 #define SPI_CS_MASK	0x80000000
254 
255 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
256 {
257 	return bus == 0 && cs == 0;
258 }
259 
260 void spi_cs_activate(struct spi_slave *slave)
261 {
262 	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
263 
264 	iopd->dat &= ~SPI_CS_MASK;
265 }
266 
267 void spi_cs_deactivate(struct spi_slave *slave)
268 {
269 	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
270 
271 	iopd->dat |=  SPI_CS_MASK;
272 }
273 #endif /* CONFIG_HARD_SPI */
274 
275 #if defined(CONFIG_OF_BOARD_SETUP)
276 void ft_board_setup(void *blob, bd_t *bd)
277 {
278 	ft_cpu_setup(blob, bd);
279 #ifdef CONFIG_PCI
280 	ft_pci_setup(blob, bd);
281 #endif
282 }
283 #endif
284