1 /* 2 * (C) Copyright 2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 */ 24 25 #include <common.h> 26 #include <ioports.h> 27 #include <mpc83xx.h> 28 #include <asm/mpc8349_pci.h> 29 #include <i2c.h> 30 #include <spi.h> 31 #include <spd.h> 32 #include <miiphy.h> 33 #if defined(CONFIG_SPD_EEPROM) 34 #include <spd_sdram.h> 35 #endif 36 #if defined(CONFIG_OF_LIBFDT) 37 #include <libfdt.h> 38 #endif 39 40 int fixed_sdram(void); 41 void sdram_init(void); 42 43 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) 44 void ddr_enable_ecc(unsigned int dram_size); 45 #endif 46 47 int board_early_init_f (void) 48 { 49 volatile u8* bcsr = (volatile u8*)CFG_BCSR; 50 51 /* Enable flash write */ 52 bcsr[1] &= ~0x01; 53 54 #ifdef CFG_USE_MPC834XSYS_USB_PHY 55 /* Use USB PHY on SYS board */ 56 bcsr[5] |= 0x02; 57 #endif 58 59 return 0; 60 } 61 62 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) 63 64 long int initdram (int board_type) 65 { 66 volatile immap_t *im = (immap_t *)CFG_IMMR; 67 u32 msize = 0; 68 69 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 70 return -1; 71 72 /* DDR SDRAM - Main SODIMM */ 73 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; 74 #if defined(CONFIG_SPD_EEPROM) 75 msize = spd_sdram(); 76 #else 77 msize = fixed_sdram(); 78 #endif 79 /* 80 * Initialize SDRAM if it is on local bus. 81 */ 82 sdram_init(); 83 84 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 85 /* 86 * Initialize and enable DDR ECC. 87 */ 88 ddr_enable_ecc(msize * 1024 * 1024); 89 #endif 90 91 /* return total bus SDRAM size(bytes) -- DDR */ 92 return (msize * 1024 * 1024); 93 } 94 95 #if !defined(CONFIG_SPD_EEPROM) 96 /************************************************************************* 97 * fixed sdram init -- doesn't use serial presence detect. 98 ************************************************************************/ 99 int fixed_sdram(void) 100 { 101 volatile immap_t *im = (immap_t *)CFG_IMMR; 102 u32 msize = 0; 103 u32 ddr_size; 104 u32 ddr_size_log2; 105 106 msize = CFG_DDR_SIZE; 107 for (ddr_size = msize << 20, ddr_size_log2 = 0; 108 (ddr_size > 1); 109 ddr_size = ddr_size>>1, ddr_size_log2++) { 110 if (ddr_size & 1) { 111 return -1; 112 } 113 } 114 im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); 115 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 116 117 #if (CFG_DDR_SIZE != 256) 118 #warning Currenly any ddr size other than 256 is not supported 119 #endif 120 #ifdef CONFIG_DDR_II 121 im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS; 122 im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG; 123 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 124 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 125 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 126 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 127 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 128 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 129 im->ddr.sdram_mode = CFG_DDR_MODE; 130 im->ddr.sdram_mode2 = CFG_DDR_MODE2; 131 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 132 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; 133 #else 134 im->ddr.csbnds[2].csbnds = 0x0000000f; 135 im->ddr.cs_config[2] = CFG_DDR_CONFIG; 136 137 /* currently we use only one CS, so disable the other banks */ 138 im->ddr.cs_config[0] = 0; 139 im->ddr.cs_config[1] = 0; 140 im->ddr.cs_config[3] = 0; 141 142 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 143 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 144 145 im->ddr.sdram_cfg = 146 SDRAM_CFG_SREN 147 #if defined(CONFIG_DDR_2T_TIMING) 148 | SDRAM_CFG_2T_EN 149 #endif 150 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; 151 #if defined (CONFIG_DDR_32BIT) 152 /* for 32-bit mode burst length is 8 */ 153 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); 154 #endif 155 im->ddr.sdram_mode = CFG_DDR_MODE; 156 157 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 158 #endif 159 udelay(200); 160 161 /* enable DDR controller */ 162 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 163 return msize; 164 } 165 #endif/*!CFG_SPD_EEPROM*/ 166 167 168 int checkboard (void) 169 { 170 puts("Board: Freescale MPC8349EMDS\n"); 171 return 0; 172 } 173 174 /* 175 * if MPC8349EMDS is soldered with SDRAM 176 */ 177 #if defined(CFG_BR2_PRELIM) \ 178 && defined(CFG_OR2_PRELIM) \ 179 && defined(CFG_LBLAWBAR2_PRELIM) \ 180 && defined(CFG_LBLAWAR2_PRELIM) 181 /* 182 * Initialize SDRAM memory on the Local Bus. 183 */ 184 185 void sdram_init(void) 186 { 187 volatile immap_t *immap = (immap_t *)CFG_IMMR; 188 volatile lbus83xx_t *lbc= &immap->lbus; 189 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 190 191 /* 192 * Setup SDRAM Base and Option Registers, already done in cpu_init.c 193 */ 194 195 /* setup mtrpt, lsrt and lbcr for LB bus */ 196 lbc->lbcr = CFG_LBC_LBCR; 197 lbc->mrtpr = CFG_LBC_MRTPR; 198 lbc->lsrt = CFG_LBC_LSRT; 199 asm("sync"); 200 201 /* 202 * Configure the SDRAM controller Machine Mode Register. 203 */ 204 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ 205 206 lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ 207 asm("sync"); 208 *sdram_addr = 0xff; 209 udelay(100); 210 211 lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ 212 asm("sync"); 213 /*1 times*/ 214 *sdram_addr = 0xff; 215 udelay(100); 216 /*2 times*/ 217 *sdram_addr = 0xff; 218 udelay(100); 219 /*3 times*/ 220 *sdram_addr = 0xff; 221 udelay(100); 222 /*4 times*/ 223 *sdram_addr = 0xff; 224 udelay(100); 225 /*5 times*/ 226 *sdram_addr = 0xff; 227 udelay(100); 228 /*6 times*/ 229 *sdram_addr = 0xff; 230 udelay(100); 231 /*7 times*/ 232 *sdram_addr = 0xff; 233 udelay(100); 234 /*8 times*/ 235 *sdram_addr = 0xff; 236 udelay(100); 237 238 /* 0x58636733; mode register write operation */ 239 lbc->lsdmr = CFG_LBC_LSDMR_4; 240 asm("sync"); 241 *sdram_addr = 0xff; 242 udelay(100); 243 244 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ 245 asm("sync"); 246 *sdram_addr = 0xff; 247 udelay(100); 248 } 249 #else 250 void sdram_init(void) 251 { 252 } 253 #endif 254 255 /* 256 * The following are used to control the SPI chip selects for the SPI command. 257 */ 258 #ifdef CONFIG_HARD_SPI 259 260 #define SPI_CS_MASK 0x80000000 261 262 void spi_eeprom_chipsel(int cs) 263 { 264 volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; 265 266 if (cs) 267 iopd->dat &= ~SPI_CS_MASK; 268 else 269 iopd->dat |= SPI_CS_MASK; 270 } 271 272 /* 273 * The SPI command uses this table of functions for controlling the SPI 274 * chip selects. 275 */ 276 spi_chipsel_type spi_chipsel[] = { 277 spi_eeprom_chipsel, 278 }; 279 int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); 280 281 #endif /* CONFIG_HARD_SPI */ 282 283 #if defined(CONFIG_OF_BOARD_SETUP) 284 void ft_board_setup(void *blob, bd_t *bd) 285 { 286 ft_cpu_setup(blob, bd); 287 #ifdef CONFIG_PCI 288 ft_pci_setup(blob, bd); 289 #endif 290 } 291 #endif 292