1 /*
2  * (C) Copyright 2006
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <ioports.h>
10 #include <mpc83xx.h>
11 #include <asm/mpc8349_pci.h>
12 #include <i2c.h>
13 #include <spi.h>
14 #include <miiphy.h>
15 #ifdef CONFIG_SYS_FSL_DDR2
16 #include <fsl_ddr_sdram.h>
17 #else
18 #include <spd_sdram.h>
19 #endif
20 
21 #if defined(CONFIG_OF_LIBFDT)
22 #include <libfdt.h>
23 #endif
24 
25 DECLARE_GLOBAL_DATA_PTR;
26 
27 int fixed_sdram(void);
28 void sdram_init(void);
29 
30 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
31 void ddr_enable_ecc(unsigned int dram_size);
32 #endif
33 
34 int board_early_init_f (void)
35 {
36 	volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
37 
38 	/* Enable flash write */
39 	bcsr[1] &= ~0x01;
40 
41 #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
42 	/* Use USB PHY on SYS board */
43 	bcsr[5] |= 0x02;
44 #endif
45 
46 	return 0;
47 }
48 
49 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
50 
51 int dram_init(void)
52 {
53 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
54 	phys_size_t msize = 0;
55 
56 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
57 		return -ENXIO;
58 
59 	/* DDR SDRAM - Main SODIMM */
60 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
61 #if defined(CONFIG_SPD_EEPROM)
62 #ifndef CONFIG_SYS_FSL_DDR2
63 	msize = spd_sdram() * 1024 * 1024;
64 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
65 	ddr_enable_ecc(msize);
66 #endif
67 #else
68 	msize = fsl_ddr_sdram();
69 #endif
70 #else
71 	msize = fixed_sdram() * 1024 * 1024;
72 #endif
73 	/*
74 	 * Initialize SDRAM if it is on local bus.
75 	 */
76 	sdram_init();
77 
78 	/* set total bus SDRAM size(bytes)  -- DDR */
79 	gd->ram_size = msize;
80 
81 	return 0;
82 }
83 
84 #if !defined(CONFIG_SPD_EEPROM)
85 /*************************************************************************
86  *  fixed sdram init -- doesn't use serial presence detect.
87  ************************************************************************/
88 int fixed_sdram(void)
89 {
90 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
91 	u32 msize = CONFIG_SYS_DDR_SIZE;
92 	u32 ddr_size = msize << 20;	/* DDR size in bytes */
93 	u32 ddr_size_log2 = __ilog2(ddr_size);
94 
95 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
96 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
97 
98 #if (CONFIG_SYS_DDR_SIZE != 256)
99 #warning Currenly any ddr size other than 256 is not supported
100 #endif
101 #ifdef CONFIG_DDR_II
102 	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
103 	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
104 	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
105 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
106 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
107 	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
108 	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
109 	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
110 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
111 	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
112 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
113 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
114 #else
115 
116 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
117 #warning Chip select bounds is only configurable in 16MB increments
118 #endif
119 	im->ddr.csbnds[2].csbnds =
120 		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
121 		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
122 				CSBNDS_EA_SHIFT) & CSBNDS_EA);
123 	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
124 
125 	/* currently we use only one CS, so disable the other banks */
126 	im->ddr.cs_config[0] = 0;
127 	im->ddr.cs_config[1] = 0;
128 	im->ddr.cs_config[3] = 0;
129 
130 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
131 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
132 
133 	im->ddr.sdram_cfg =
134 		SDRAM_CFG_SREN
135 #if defined(CONFIG_DDR_2T_TIMING)
136 		| SDRAM_CFG_2T_EN
137 #endif
138 		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
139 #if defined (CONFIG_DDR_32BIT)
140 	/* for 32-bit mode burst length is 8 */
141 	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
142 #endif
143 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
144 
145 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
146 #endif
147 	udelay(200);
148 
149 	/* enable DDR controller */
150 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
151 	return msize;
152 }
153 #endif/*!CONFIG_SYS_SPD_EEPROM*/
154 
155 
156 int checkboard (void)
157 {
158 	/*
159 	 * Warning: do not read the BCSR registers here
160 	 *
161 	 * There is a timing bug in the 8349E and 8349EA BCSR code
162 	 * version 1.2 (read from BCSR 11) that will cause the CFI
163 	 * flash initialization code to overwrite BCSR 0, disabling
164 	 * the serial ports and gigabit ethernet
165 	 */
166 
167 	puts("Board: Freescale MPC8349EMDS\n");
168 	return 0;
169 }
170 
171 /*
172  * if MPC8349EMDS is soldered with SDRAM
173  */
174 #if defined(CONFIG_SYS_BR2_PRELIM)  \
175 	&& defined(CONFIG_SYS_OR2_PRELIM) \
176 	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
177 	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
178 /*
179  * Initialize SDRAM memory on the Local Bus.
180  */
181 
182 void sdram_init(void)
183 {
184 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
185 	volatile fsl_lbc_t *lbc = &immap->im_lbc;
186 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
187 
188 	/*
189 	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
190 	 */
191 
192 	/* setup mtrpt, lsrt and lbcr for LB bus */
193 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
194 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
195 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
196 	asm("sync");
197 
198 	/*
199 	 * Configure the SDRAM controller Machine Mode Register.
200 	 */
201 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
202 
203 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
204 	asm("sync");
205 	*sdram_addr = 0xff;
206 	udelay(100);
207 
208 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
209 	asm("sync");
210 	/*1 times*/
211 	*sdram_addr = 0xff;
212 	udelay(100);
213 	/*2 times*/
214 	*sdram_addr = 0xff;
215 	udelay(100);
216 	/*3 times*/
217 	*sdram_addr = 0xff;
218 	udelay(100);
219 	/*4 times*/
220 	*sdram_addr = 0xff;
221 	udelay(100);
222 	/*5 times*/
223 	*sdram_addr = 0xff;
224 	udelay(100);
225 	/*6 times*/
226 	*sdram_addr = 0xff;
227 	udelay(100);
228 	/*7 times*/
229 	*sdram_addr = 0xff;
230 	udelay(100);
231 	/*8 times*/
232 	*sdram_addr = 0xff;
233 	udelay(100);
234 
235 	/* 0x58636733; mode register write operation */
236 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
237 	asm("sync");
238 	*sdram_addr = 0xff;
239 	udelay(100);
240 
241 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
242 	asm("sync");
243 	*sdram_addr = 0xff;
244 	udelay(100);
245 }
246 #else
247 void sdram_init(void)
248 {
249 }
250 #endif
251 
252 /*
253  * The following are used to control the SPI chip selects for the SPI command.
254  */
255 #ifdef CONFIG_MPC8XXX_SPI
256 
257 #define SPI_CS_MASK	0x80000000
258 
259 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
260 {
261 	return bus == 0 && cs == 0;
262 }
263 
264 void spi_cs_activate(struct spi_slave *slave)
265 {
266 	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
267 
268 	iopd->dat &= ~SPI_CS_MASK;
269 }
270 
271 void spi_cs_deactivate(struct spi_slave *slave)
272 {
273 	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
274 
275 	iopd->dat |=  SPI_CS_MASK;
276 }
277 #endif /* CONFIG_HARD_SPI */
278 
279 #if defined(CONFIG_OF_BOARD_SETUP)
280 int ft_board_setup(void *blob, bd_t *bd)
281 {
282 	ft_cpu_setup(blob, bd);
283 #ifdef CONFIG_PCI
284 	ft_pci_setup(blob, bd);
285 #endif
286 
287 	return 0;
288 }
289 #endif
290