1 /* 2 * (C) Copyright 2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 */ 24 25 #include <common.h> 26 #include <ioports.h> 27 #include <mpc83xx.h> 28 #include <asm/mpc8349_pci.h> 29 #include <i2c.h> 30 #include <spd.h> 31 #include <miiphy.h> 32 #if defined(CONFIG_SPD_EEPROM) 33 #include <spd_sdram.h> 34 #endif 35 #if defined(CONFIG_OF_FLAT_TREE) 36 #include <ft_build.h> 37 #elif defined(CONFIG_OF_LIBFDT) 38 #include <libfdt.h> 39 #endif 40 41 int fixed_sdram(void); 42 void sdram_init(void); 43 44 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) 45 void ddr_enable_ecc(unsigned int dram_size); 46 #endif 47 48 int board_early_init_f (void) 49 { 50 volatile u8* bcsr = (volatile u8*)CFG_BCSR; 51 52 /* Enable flash write */ 53 bcsr[1] &= ~0x01; 54 55 #ifdef CFG_USE_MPC834XSYS_USB_PHY 56 /* Use USB PHY on SYS board */ 57 bcsr[5] |= 0x02; 58 #endif 59 60 return 0; 61 } 62 63 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) 64 65 long int initdram (int board_type) 66 { 67 volatile immap_t *im = (immap_t *)CFG_IMMR; 68 u32 msize = 0; 69 70 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 71 return -1; 72 73 /* DDR SDRAM - Main SODIMM */ 74 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; 75 #if defined(CONFIG_SPD_EEPROM) 76 msize = spd_sdram(); 77 #else 78 msize = fixed_sdram(); 79 #endif 80 /* 81 * Initialize SDRAM if it is on local bus. 82 */ 83 sdram_init(); 84 85 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 86 /* 87 * Initialize and enable DDR ECC. 88 */ 89 ddr_enable_ecc(msize * 1024 * 1024); 90 #endif 91 92 /* return total bus SDRAM size(bytes) -- DDR */ 93 return (msize * 1024 * 1024); 94 } 95 96 #if !defined(CONFIG_SPD_EEPROM) 97 /************************************************************************* 98 * fixed sdram init -- doesn't use serial presence detect. 99 ************************************************************************/ 100 int fixed_sdram(void) 101 { 102 volatile immap_t *im = (immap_t *)CFG_IMMR; 103 u32 msize = 0; 104 u32 ddr_size; 105 u32 ddr_size_log2; 106 107 msize = CFG_DDR_SIZE; 108 for (ddr_size = msize << 20, ddr_size_log2 = 0; 109 (ddr_size > 1); 110 ddr_size = ddr_size>>1, ddr_size_log2++) { 111 if (ddr_size & 1) { 112 return -1; 113 } 114 } 115 im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); 116 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 117 118 #if (CFG_DDR_SIZE != 256) 119 #warning Currenly any ddr size other than 256 is not supported 120 #endif 121 #ifdef CONFIG_DDR_II 122 im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS; 123 im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG; 124 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 125 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 126 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 127 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 128 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 129 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 130 im->ddr.sdram_mode = CFG_DDR_MODE; 131 im->ddr.sdram_mode2 = CFG_DDR_MODE2; 132 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 133 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; 134 #else 135 im->ddr.csbnds[2].csbnds = 0x0000000f; 136 im->ddr.cs_config[2] = CFG_DDR_CONFIG; 137 138 /* currently we use only one CS, so disable the other banks */ 139 im->ddr.cs_config[0] = 0; 140 im->ddr.cs_config[1] = 0; 141 im->ddr.cs_config[3] = 0; 142 143 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 144 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 145 146 im->ddr.sdram_cfg = 147 SDRAM_CFG_SREN 148 #if defined(CONFIG_DDR_2T_TIMING) 149 | SDRAM_CFG_2T_EN 150 #endif 151 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; 152 #if defined (CONFIG_DDR_32BIT) 153 /* for 32-bit mode burst length is 8 */ 154 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); 155 #endif 156 im->ddr.sdram_mode = CFG_DDR_MODE; 157 158 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 159 #endif 160 udelay(200); 161 162 /* enable DDR controller */ 163 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 164 return msize; 165 } 166 #endif/*!CFG_SPD_EEPROM*/ 167 168 169 int checkboard (void) 170 { 171 puts("Board: Freescale MPC8349EMDS\n"); 172 return 0; 173 } 174 175 /* 176 * if MPC8349EMDS is soldered with SDRAM 177 */ 178 #if defined(CFG_BR2_PRELIM) \ 179 && defined(CFG_OR2_PRELIM) \ 180 && defined(CFG_LBLAWBAR2_PRELIM) \ 181 && defined(CFG_LBLAWAR2_PRELIM) 182 /* 183 * Initialize SDRAM memory on the Local Bus. 184 */ 185 186 void sdram_init(void) 187 { 188 volatile immap_t *immap = (immap_t *)CFG_IMMR; 189 volatile lbus83xx_t *lbc= &immap->lbus; 190 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 191 192 /* 193 * Setup SDRAM Base and Option Registers, already done in cpu_init.c 194 */ 195 196 /* setup mtrpt, lsrt and lbcr for LB bus */ 197 lbc->lbcr = CFG_LBC_LBCR; 198 lbc->mrtpr = CFG_LBC_MRTPR; 199 lbc->lsrt = CFG_LBC_LSRT; 200 asm("sync"); 201 202 /* 203 * Configure the SDRAM controller Machine Mode Register. 204 */ 205 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ 206 207 lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ 208 asm("sync"); 209 *sdram_addr = 0xff; 210 udelay(100); 211 212 lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ 213 asm("sync"); 214 /*1 times*/ 215 *sdram_addr = 0xff; 216 udelay(100); 217 /*2 times*/ 218 *sdram_addr = 0xff; 219 udelay(100); 220 /*3 times*/ 221 *sdram_addr = 0xff; 222 udelay(100); 223 /*4 times*/ 224 *sdram_addr = 0xff; 225 udelay(100); 226 /*5 times*/ 227 *sdram_addr = 0xff; 228 udelay(100); 229 /*6 times*/ 230 *sdram_addr = 0xff; 231 udelay(100); 232 /*7 times*/ 233 *sdram_addr = 0xff; 234 udelay(100); 235 /*8 times*/ 236 *sdram_addr = 0xff; 237 udelay(100); 238 239 /* 0x58636733; mode register write operation */ 240 lbc->lsdmr = CFG_LBC_LSDMR_4; 241 asm("sync"); 242 *sdram_addr = 0xff; 243 udelay(100); 244 245 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ 246 asm("sync"); 247 *sdram_addr = 0xff; 248 udelay(100); 249 } 250 #else 251 void sdram_init(void) 252 { 253 } 254 #endif 255 256 #if defined(CONFIG_OF_BOARD_SETUP) 257 void ft_board_setup(void *blob, bd_t *bd) 258 { 259 #if defined(CONFIG_OF_FLAT_TREE) 260 u32 *p; 261 int len; 262 263 p = ft_get_prop(blob, "/memory/reg", &len); 264 if (p != NULL) { 265 *p++ = cpu_to_be32(bd->bi_memstart); 266 *p = cpu_to_be32(bd->bi_memsize); 267 } 268 #endif 269 ft_cpu_setup(blob, bd); 270 #ifdef CONFIG_PCI 271 ft_pci_setup(blob, bd); 272 #endif 273 } 274 #endif 275