1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 #include <common.h> 8 #include <ioports.h> 9 #include <mpc83xx.h> 10 #include <asm/mpc8349_pci.h> 11 #include <i2c.h> 12 #include <spi.h> 13 #include <miiphy.h> 14 #ifdef CONFIG_SYS_FSL_DDR2 15 #include <fsl_ddr_sdram.h> 16 #else 17 #include <spd_sdram.h> 18 #endif 19 20 #if defined(CONFIG_OF_LIBFDT) 21 #include <linux/libfdt.h> 22 #endif 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 int fixed_sdram(void); 27 void sdram_init(void); 28 29 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx) 30 void ddr_enable_ecc(unsigned int dram_size); 31 #endif 32 33 int board_early_init_f (void) 34 { 35 volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR; 36 37 /* Enable flash write */ 38 bcsr[1] &= ~0x01; 39 40 #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY 41 /* Use USB PHY on SYS board */ 42 bcsr[5] |= 0x02; 43 #endif 44 45 return 0; 46 } 47 48 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) 49 50 int dram_init(void) 51 { 52 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 53 phys_size_t msize = 0; 54 55 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 56 return -ENXIO; 57 58 /* DDR SDRAM - Main SODIMM */ 59 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 60 #if defined(CONFIG_SPD_EEPROM) 61 #ifndef CONFIG_SYS_FSL_DDR2 62 msize = spd_sdram() * 1024 * 1024; 63 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 64 ddr_enable_ecc(msize); 65 #endif 66 #else 67 msize = fsl_ddr_sdram(); 68 #endif 69 #else 70 msize = fixed_sdram() * 1024 * 1024; 71 #endif 72 /* 73 * Initialize SDRAM if it is on local bus. 74 */ 75 sdram_init(); 76 77 /* set total bus SDRAM size(bytes) -- DDR */ 78 gd->ram_size = msize; 79 80 return 0; 81 } 82 83 #if !defined(CONFIG_SPD_EEPROM) 84 /************************************************************************* 85 * fixed sdram init -- doesn't use serial presence detect. 86 ************************************************************************/ 87 int fixed_sdram(void) 88 { 89 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 90 u32 msize = CONFIG_SYS_DDR_SIZE; 91 u32 ddr_size = msize << 20; /* DDR size in bytes */ 92 u32 ddr_size_log2 = __ilog2(ddr_size); 93 94 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 95 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 96 97 #if (CONFIG_SYS_DDR_SIZE != 256) 98 #warning Currenly any ddr size other than 256 is not supported 99 #endif 100 #ifdef CONFIG_DDR_II 101 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS; 102 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; 103 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 104 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 105 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 106 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 107 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; 108 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; 109 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 110 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; 111 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 112 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; 113 #else 114 115 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) 116 #warning Chip select bounds is only configurable in 16MB increments 117 #endif 118 im->ddr.csbnds[2].csbnds = 119 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | 120 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> 121 CSBNDS_EA_SHIFT) & CSBNDS_EA); 122 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; 123 124 /* currently we use only one CS, so disable the other banks */ 125 im->ddr.cs_config[0] = 0; 126 im->ddr.cs_config[1] = 0; 127 im->ddr.cs_config[3] = 0; 128 129 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 130 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 131 132 im->ddr.sdram_cfg = 133 SDRAM_CFG_SREN 134 #if defined(CONFIG_DDR_2T_TIMING) 135 | SDRAM_CFG_2T_EN 136 #endif 137 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; 138 #if defined (CONFIG_DDR_32BIT) 139 /* for 32-bit mode burst length is 8 */ 140 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); 141 #endif 142 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 143 144 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 145 #endif 146 udelay(200); 147 148 /* enable DDR controller */ 149 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 150 return msize; 151 } 152 #endif/*!CONFIG_SYS_SPD_EEPROM*/ 153 154 155 int checkboard (void) 156 { 157 /* 158 * Warning: do not read the BCSR registers here 159 * 160 * There is a timing bug in the 8349E and 8349EA BCSR code 161 * version 1.2 (read from BCSR 11) that will cause the CFI 162 * flash initialization code to overwrite BCSR 0, disabling 163 * the serial ports and gigabit ethernet 164 */ 165 166 puts("Board: Freescale MPC8349EMDS\n"); 167 return 0; 168 } 169 170 /* 171 * if MPC8349EMDS is soldered with SDRAM 172 */ 173 #if defined(CONFIG_SYS_BR2_PRELIM) \ 174 && defined(CONFIG_SYS_OR2_PRELIM) \ 175 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ 176 && defined(CONFIG_SYS_LBLAWAR2_PRELIM) 177 /* 178 * Initialize SDRAM memory on the Local Bus. 179 */ 180 181 void sdram_init(void) 182 { 183 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 184 volatile fsl_lbc_t *lbc = &immap->im_lbc; 185 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 186 187 /* 188 * Setup SDRAM Base and Option Registers, already done in cpu_init.c 189 */ 190 191 /* setup mtrpt, lsrt and lbcr for LB bus */ 192 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 193 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 194 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 195 asm("sync"); 196 197 /* 198 * Configure the SDRAM controller Machine Mode Register. 199 */ 200 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ 201 202 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ 203 asm("sync"); 204 *sdram_addr = 0xff; 205 udelay(100); 206 207 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ 208 asm("sync"); 209 /*1 times*/ 210 *sdram_addr = 0xff; 211 udelay(100); 212 /*2 times*/ 213 *sdram_addr = 0xff; 214 udelay(100); 215 /*3 times*/ 216 *sdram_addr = 0xff; 217 udelay(100); 218 /*4 times*/ 219 *sdram_addr = 0xff; 220 udelay(100); 221 /*5 times*/ 222 *sdram_addr = 0xff; 223 udelay(100); 224 /*6 times*/ 225 *sdram_addr = 0xff; 226 udelay(100); 227 /*7 times*/ 228 *sdram_addr = 0xff; 229 udelay(100); 230 /*8 times*/ 231 *sdram_addr = 0xff; 232 udelay(100); 233 234 /* 0x58636733; mode register write operation */ 235 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; 236 asm("sync"); 237 *sdram_addr = 0xff; 238 udelay(100); 239 240 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ 241 asm("sync"); 242 *sdram_addr = 0xff; 243 udelay(100); 244 } 245 #else 246 void sdram_init(void) 247 { 248 } 249 #endif 250 251 /* 252 * The following are used to control the SPI chip selects for the SPI command. 253 */ 254 #ifdef CONFIG_MPC8XXX_SPI 255 256 #define SPI_CS_MASK 0x80000000 257 258 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 259 { 260 return bus == 0 && cs == 0; 261 } 262 263 void spi_cs_activate(struct spi_slave *slave) 264 { 265 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; 266 267 iopd->dat &= ~SPI_CS_MASK; 268 } 269 270 void spi_cs_deactivate(struct spi_slave *slave) 271 { 272 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; 273 274 iopd->dat |= SPI_CS_MASK; 275 } 276 #endif 277 278 #if defined(CONFIG_OF_BOARD_SETUP) 279 int ft_board_setup(void *blob, bd_t *bd) 280 { 281 ft_cpu_setup(blob, bd); 282 #ifdef CONFIG_PCI 283 ft_pci_setup(blob, bd); 284 #endif 285 286 return 0; 287 } 288 #endif 289