1e58fe957SKim Phillips /* 2e58fe957SKim Phillips * (C) Copyright 2006 3e58fe957SKim Phillips * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4e58fe957SKim Phillips * 5e58fe957SKim Phillips * See file CREDITS for list of people who contributed to this 6e58fe957SKim Phillips * project. 7e58fe957SKim Phillips * 8e58fe957SKim Phillips * This program is free software; you can redistribute it and/or 9e58fe957SKim Phillips * modify it under the terms of the GNU General Public License as 10e58fe957SKim Phillips * published by the Free Software Foundation; either version 2 of 11e58fe957SKim Phillips * the License, or (at your option) any later version. 12e58fe957SKim Phillips * 13e58fe957SKim Phillips * This program is distributed in the hope that it will be useful, 14e58fe957SKim Phillips * but WITHOUT ANY WARRANTY; without even the implied warranty of 15e58fe957SKim Phillips * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16e58fe957SKim Phillips * GNU General Public License for more details. 17e58fe957SKim Phillips * 18e58fe957SKim Phillips * You should have received a copy of the GNU General Public License 19e58fe957SKim Phillips * along with this program; if not, write to the Free Software 20e58fe957SKim Phillips * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21e58fe957SKim Phillips * MA 02111-1307 USA 22e58fe957SKim Phillips * 23e58fe957SKim Phillips */ 24e58fe957SKim Phillips 25e58fe957SKim Phillips #include <common.h> 26e58fe957SKim Phillips #include <ioports.h> 27e58fe957SKim Phillips #include <mpc83xx.h> 28e58fe957SKim Phillips #include <asm/mpc8349_pci.h> 29e58fe957SKim Phillips #include <i2c.h> 3080ddd226SBen Warren #include <spi.h> 31e58fe957SKim Phillips #include <miiphy.h> 32e58fe957SKim Phillips #include <spd_sdram.h> 33a30a549aSJon Loeliger 34b3458d2cSKim Phillips #if defined(CONFIG_OF_LIBFDT) 35e58fe957SKim Phillips #include <libfdt.h> 36e58fe957SKim Phillips #endif 37e58fe957SKim Phillips 38e58fe957SKim Phillips int fixed_sdram(void); 39e58fe957SKim Phillips void sdram_init(void); 40e58fe957SKim Phillips 41e58fe957SKim Phillips #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) 42e58fe957SKim Phillips void ddr_enable_ecc(unsigned int dram_size); 43e58fe957SKim Phillips #endif 44e58fe957SKim Phillips 45e58fe957SKim Phillips int board_early_init_f (void) 46e58fe957SKim Phillips { 47e58fe957SKim Phillips volatile u8* bcsr = (volatile u8*)CFG_BCSR; 48e58fe957SKim Phillips 49e58fe957SKim Phillips /* Enable flash write */ 50e58fe957SKim Phillips bcsr[1] &= ~0x01; 51e58fe957SKim Phillips 52e58fe957SKim Phillips #ifdef CFG_USE_MPC834XSYS_USB_PHY 53e58fe957SKim Phillips /* Use USB PHY on SYS board */ 54e58fe957SKim Phillips bcsr[5] |= 0x02; 55e58fe957SKim Phillips #endif 56e58fe957SKim Phillips 57e58fe957SKim Phillips return 0; 58e58fe957SKim Phillips } 59e58fe957SKim Phillips 60e58fe957SKim Phillips #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) 61e58fe957SKim Phillips 62e58fe957SKim Phillips long int initdram (int board_type) 63e58fe957SKim Phillips { 64e58fe957SKim Phillips volatile immap_t *im = (immap_t *)CFG_IMMR; 65e58fe957SKim Phillips u32 msize = 0; 66e58fe957SKim Phillips 67e58fe957SKim Phillips if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 68e58fe957SKim Phillips return -1; 69e58fe957SKim Phillips 70e58fe957SKim Phillips /* DDR SDRAM - Main SODIMM */ 71e58fe957SKim Phillips im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; 72e58fe957SKim Phillips #if defined(CONFIG_SPD_EEPROM) 73e58fe957SKim Phillips msize = spd_sdram(); 74e58fe957SKim Phillips #else 75e58fe957SKim Phillips msize = fixed_sdram(); 76e58fe957SKim Phillips #endif 77e58fe957SKim Phillips /* 78e58fe957SKim Phillips * Initialize SDRAM if it is on local bus. 79e58fe957SKim Phillips */ 80e58fe957SKim Phillips sdram_init(); 81e58fe957SKim Phillips 82e58fe957SKim Phillips #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 83e58fe957SKim Phillips /* 84e58fe957SKim Phillips * Initialize and enable DDR ECC. 85e58fe957SKim Phillips */ 86e58fe957SKim Phillips ddr_enable_ecc(msize * 1024 * 1024); 87e58fe957SKim Phillips #endif 88e58fe957SKim Phillips 89e58fe957SKim Phillips /* return total bus SDRAM size(bytes) -- DDR */ 90e58fe957SKim Phillips return (msize * 1024 * 1024); 91e58fe957SKim Phillips } 92e58fe957SKim Phillips 93e58fe957SKim Phillips #if !defined(CONFIG_SPD_EEPROM) 94e58fe957SKim Phillips /************************************************************************* 95e58fe957SKim Phillips * fixed sdram init -- doesn't use serial presence detect. 96e58fe957SKim Phillips ************************************************************************/ 97e58fe957SKim Phillips int fixed_sdram(void) 98e58fe957SKim Phillips { 99e58fe957SKim Phillips volatile immap_t *im = (immap_t *)CFG_IMMR; 100e58fe957SKim Phillips u32 msize = 0; 101e58fe957SKim Phillips u32 ddr_size; 102e58fe957SKim Phillips u32 ddr_size_log2; 103e58fe957SKim Phillips 104e58fe957SKim Phillips msize = CFG_DDR_SIZE; 105e58fe957SKim Phillips for (ddr_size = msize << 20, ddr_size_log2 = 0; 106e58fe957SKim Phillips (ddr_size > 1); 107e58fe957SKim Phillips ddr_size = ddr_size>>1, ddr_size_log2++) { 108e58fe957SKim Phillips if (ddr_size & 1) { 109e58fe957SKim Phillips return -1; 110e58fe957SKim Phillips } 111e58fe957SKim Phillips } 112e58fe957SKim Phillips im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); 113e58fe957SKim Phillips im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 114e58fe957SKim Phillips 115e58fe957SKim Phillips #if (CFG_DDR_SIZE != 256) 116e58fe957SKim Phillips #warning Currenly any ddr size other than 256 is not supported 117e58fe957SKim Phillips #endif 118e58fe957SKim Phillips #ifdef CONFIG_DDR_II 119e58fe957SKim Phillips im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS; 120e58fe957SKim Phillips im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG; 121e58fe957SKim Phillips im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 122e58fe957SKim Phillips im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 123e58fe957SKim Phillips im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 124e58fe957SKim Phillips im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 125e58fe957SKim Phillips im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 126e58fe957SKim Phillips im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 127e58fe957SKim Phillips im->ddr.sdram_mode = CFG_DDR_MODE; 128e58fe957SKim Phillips im->ddr.sdram_mode2 = CFG_DDR_MODE2; 129e58fe957SKim Phillips im->ddr.sdram_interval = CFG_DDR_INTERVAL; 130e58fe957SKim Phillips im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; 131e58fe957SKim Phillips #else 132e58fe957SKim Phillips im->ddr.csbnds[2].csbnds = 0x0000000f; 133e58fe957SKim Phillips im->ddr.cs_config[2] = CFG_DDR_CONFIG; 134e58fe957SKim Phillips 135e58fe957SKim Phillips /* currently we use only one CS, so disable the other banks */ 136e58fe957SKim Phillips im->ddr.cs_config[0] = 0; 137e58fe957SKim Phillips im->ddr.cs_config[1] = 0; 138e58fe957SKim Phillips im->ddr.cs_config[3] = 0; 139e58fe957SKim Phillips 140e58fe957SKim Phillips im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 141e58fe957SKim Phillips im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 142e58fe957SKim Phillips 143e58fe957SKim Phillips im->ddr.sdram_cfg = 144e58fe957SKim Phillips SDRAM_CFG_SREN 145e58fe957SKim Phillips #if defined(CONFIG_DDR_2T_TIMING) 146e58fe957SKim Phillips | SDRAM_CFG_2T_EN 147e58fe957SKim Phillips #endif 148e58fe957SKim Phillips | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; 149e58fe957SKim Phillips #if defined (CONFIG_DDR_32BIT) 150e58fe957SKim Phillips /* for 32-bit mode burst length is 8 */ 151e58fe957SKim Phillips im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); 152e58fe957SKim Phillips #endif 153e58fe957SKim Phillips im->ddr.sdram_mode = CFG_DDR_MODE; 154e58fe957SKim Phillips 155e58fe957SKim Phillips im->ddr.sdram_interval = CFG_DDR_INTERVAL; 156e58fe957SKim Phillips #endif 157e58fe957SKim Phillips udelay(200); 158e58fe957SKim Phillips 159e58fe957SKim Phillips /* enable DDR controller */ 160e58fe957SKim Phillips im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 161e58fe957SKim Phillips return msize; 162e58fe957SKim Phillips } 163e58fe957SKim Phillips #endif/*!CFG_SPD_EEPROM*/ 164e58fe957SKim Phillips 165e58fe957SKim Phillips 166e58fe957SKim Phillips int checkboard (void) 167e58fe957SKim Phillips { 168e58fe957SKim Phillips puts("Board: Freescale MPC8349EMDS\n"); 169e58fe957SKim Phillips return 0; 170e58fe957SKim Phillips } 171e58fe957SKim Phillips 172e58fe957SKim Phillips /* 173e58fe957SKim Phillips * if MPC8349EMDS is soldered with SDRAM 174e58fe957SKim Phillips */ 175e58fe957SKim Phillips #if defined(CFG_BR2_PRELIM) \ 176e58fe957SKim Phillips && defined(CFG_OR2_PRELIM) \ 177e58fe957SKim Phillips && defined(CFG_LBLAWBAR2_PRELIM) \ 178e58fe957SKim Phillips && defined(CFG_LBLAWAR2_PRELIM) 179e58fe957SKim Phillips /* 180e58fe957SKim Phillips * Initialize SDRAM memory on the Local Bus. 181e58fe957SKim Phillips */ 182e58fe957SKim Phillips 183e58fe957SKim Phillips void sdram_init(void) 184e58fe957SKim Phillips { 185e58fe957SKim Phillips volatile immap_t *immap = (immap_t *)CFG_IMMR; 186e58fe957SKim Phillips volatile lbus83xx_t *lbc= &immap->lbus; 187e58fe957SKim Phillips uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 188e58fe957SKim Phillips 189e58fe957SKim Phillips /* 190e58fe957SKim Phillips * Setup SDRAM Base and Option Registers, already done in cpu_init.c 191e58fe957SKim Phillips */ 192e58fe957SKim Phillips 193e58fe957SKim Phillips /* setup mtrpt, lsrt and lbcr for LB bus */ 194e58fe957SKim Phillips lbc->lbcr = CFG_LBC_LBCR; 195e58fe957SKim Phillips lbc->mrtpr = CFG_LBC_MRTPR; 196e58fe957SKim Phillips lbc->lsrt = CFG_LBC_LSRT; 197e58fe957SKim Phillips asm("sync"); 198e58fe957SKim Phillips 199e58fe957SKim Phillips /* 200e58fe957SKim Phillips * Configure the SDRAM controller Machine Mode Register. 201e58fe957SKim Phillips */ 202e58fe957SKim Phillips lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ 203e58fe957SKim Phillips 204e58fe957SKim Phillips lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ 205e58fe957SKim Phillips asm("sync"); 206e58fe957SKim Phillips *sdram_addr = 0xff; 207e58fe957SKim Phillips udelay(100); 208e58fe957SKim Phillips 209e58fe957SKim Phillips lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ 210e58fe957SKim Phillips asm("sync"); 211e58fe957SKim Phillips /*1 times*/ 212e58fe957SKim Phillips *sdram_addr = 0xff; 213e58fe957SKim Phillips udelay(100); 214e58fe957SKim Phillips /*2 times*/ 215e58fe957SKim Phillips *sdram_addr = 0xff; 216e58fe957SKim Phillips udelay(100); 217e58fe957SKim Phillips /*3 times*/ 218e58fe957SKim Phillips *sdram_addr = 0xff; 219e58fe957SKim Phillips udelay(100); 220e58fe957SKim Phillips /*4 times*/ 221e58fe957SKim Phillips *sdram_addr = 0xff; 222e58fe957SKim Phillips udelay(100); 223e58fe957SKim Phillips /*5 times*/ 224e58fe957SKim Phillips *sdram_addr = 0xff; 225e58fe957SKim Phillips udelay(100); 226e58fe957SKim Phillips /*6 times*/ 227e58fe957SKim Phillips *sdram_addr = 0xff; 228e58fe957SKim Phillips udelay(100); 229e58fe957SKim Phillips /*7 times*/ 230e58fe957SKim Phillips *sdram_addr = 0xff; 231e58fe957SKim Phillips udelay(100); 232e58fe957SKim Phillips /*8 times*/ 233e58fe957SKim Phillips *sdram_addr = 0xff; 234e58fe957SKim Phillips udelay(100); 235e58fe957SKim Phillips 236e58fe957SKim Phillips /* 0x58636733; mode register write operation */ 237e58fe957SKim Phillips lbc->lsdmr = CFG_LBC_LSDMR_4; 238e58fe957SKim Phillips asm("sync"); 239e58fe957SKim Phillips *sdram_addr = 0xff; 240e58fe957SKim Phillips udelay(100); 241e58fe957SKim Phillips 242e58fe957SKim Phillips lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ 243e58fe957SKim Phillips asm("sync"); 244e58fe957SKim Phillips *sdram_addr = 0xff; 245e58fe957SKim Phillips udelay(100); 246e58fe957SKim Phillips } 247e58fe957SKim Phillips #else 248e58fe957SKim Phillips void sdram_init(void) 249e58fe957SKim Phillips { 250e58fe957SKim Phillips } 251e58fe957SKim Phillips #endif 252e58fe957SKim Phillips 25380ddd226SBen Warren /* 25480ddd226SBen Warren * The following are used to control the SPI chip selects for the SPI command. 25580ddd226SBen Warren */ 25680ddd226SBen Warren #ifdef CONFIG_HARD_SPI 25780ddd226SBen Warren 25880ddd226SBen Warren #define SPI_CS_MASK 0x80000000 25980ddd226SBen Warren 260*d255bb0eSHaavard Skinnemoen int spi_cs_is_valid(unsigned int bus, unsigned int cs) 261*d255bb0eSHaavard Skinnemoen { 262*d255bb0eSHaavard Skinnemoen return bus == 0 && cs == 0; 263*d255bb0eSHaavard Skinnemoen } 264*d255bb0eSHaavard Skinnemoen 265*d255bb0eSHaavard Skinnemoen void spi_cs_activate(struct spi_slave *slave) 26680ddd226SBen Warren { 26780ddd226SBen Warren volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; 26880ddd226SBen Warren 26980ddd226SBen Warren iopd->dat &= ~SPI_CS_MASK; 27080ddd226SBen Warren } 27180ddd226SBen Warren 272*d255bb0eSHaavard Skinnemoen void spi_cs_deactivate(struct spi_slave *slave) 273*d255bb0eSHaavard Skinnemoen { 274*d255bb0eSHaavard Skinnemoen volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; 27580ddd226SBen Warren 276*d255bb0eSHaavard Skinnemoen iopd->dat |= SPI_CS_MASK; 277*d255bb0eSHaavard Skinnemoen } 27880ddd226SBen Warren #endif /* CONFIG_HARD_SPI */ 27980ddd226SBen Warren 280e58fe957SKim Phillips #if defined(CONFIG_OF_BOARD_SETUP) 281e58fe957SKim Phillips void ft_board_setup(void *blob, bd_t *bd) 282e58fe957SKim Phillips { 283e58fe957SKim Phillips ft_cpu_setup(blob, bd); 284e58fe957SKim Phillips #ifdef CONFIG_PCI 285e58fe957SKim Phillips ft_pci_setup(blob, bd); 286e58fe957SKim Phillips #endif 287e58fe957SKim Phillips } 288e58fe957SKim Phillips #endif 289