1 /* 2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 /* 14 * PCI Configuration space access support for MPC83xx PCI Bridge 15 */ 16 #include <asm/mmu.h> 17 #include <asm/io.h> 18 #include <common.h> 19 #include <mpc83xx.h> 20 #include <pci.h> 21 #include <i2c.h> 22 #include <asm/fsl_i2c.h> 23 #include "../common/pq-mds-pib.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 static struct pci_region pci1_regions[] = { 28 { 29 bus_start: CONFIG_SYS_PCI1_MEM_BASE, 30 phys_start: CONFIG_SYS_PCI1_MEM_PHYS, 31 size: CONFIG_SYS_PCI1_MEM_SIZE, 32 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 33 }, 34 { 35 bus_start: CONFIG_SYS_PCI1_IO_BASE, 36 phys_start: CONFIG_SYS_PCI1_IO_PHYS, 37 size: CONFIG_SYS_PCI1_IO_SIZE, 38 flags: PCI_REGION_IO 39 }, 40 { 41 bus_start: CONFIG_SYS_PCI1_MMIO_BASE, 42 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, 43 size: CONFIG_SYS_PCI1_MMIO_SIZE, 44 flags: PCI_REGION_MEM 45 }, 46 }; 47 48 #ifdef CONFIG_MPC83XX_PCI2 49 static struct pci_region pci2_regions[] = { 50 { 51 bus_start: CONFIG_SYS_PCI2_MEM_BASE, 52 phys_start: CONFIG_SYS_PCI2_MEM_PHYS, 53 size: CONFIG_SYS_PCI2_MEM_SIZE, 54 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 55 }, 56 { 57 bus_start: CONFIG_SYS_PCI2_IO_BASE, 58 phys_start: CONFIG_SYS_PCI2_IO_PHYS, 59 size: CONFIG_SYS_PCI2_IO_SIZE, 60 flags: PCI_REGION_IO 61 }, 62 { 63 bus_start: CONFIG_SYS_PCI2_MMIO_BASE, 64 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, 65 size: CONFIG_SYS_PCI2_MMIO_SIZE, 66 flags: PCI_REGION_MEM 67 }, 68 }; 69 #endif 70 71 void pci_init_board(void) 72 #ifdef CONFIG_PCISLAVE 73 { 74 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 75 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 76 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; 77 struct pci_region *reg[] = { pci1_regions }; 78 79 /* Configure PCI Local Access Windows */ 80 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 81 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; 82 83 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 84 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; 85 86 mpc83xx_pci_init(1, reg); 87 88 /* 89 * Configure PCI Inbound Translation Windows 90 */ 91 pci_ctrl[0].pitar0 = 0x0; 92 pci_ctrl[0].pibar0 = 0x0; 93 pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | 94 PIWAR_WTT_SNOOP | PIWAR_IWS_4K; 95 96 pci_ctrl[0].pitar1 = 0x0; 97 pci_ctrl[0].pibar1 = 0x0; 98 pci_ctrl[0].piebar1 = 0x0; 99 pci_ctrl[0].piwar1 &= ~PIWAR_EN; 100 101 pci_ctrl[0].pitar2 = 0x0; 102 pci_ctrl[0].pibar2 = 0x0; 103 pci_ctrl[0].piebar2 = 0x0; 104 pci_ctrl[0].piwar2 &= ~PIWAR_EN; 105 106 /* Unlock the configuration bit */ 107 mpc83xx_pcislave_unlock(0); 108 printf("PCI: Agent mode enabled\n"); 109 } 110 #else 111 { 112 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 113 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 114 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 115 #ifndef CONFIG_MPC83XX_PCI2 116 struct pci_region *reg[] = { pci1_regions }; 117 #else 118 struct pci_region *reg[] = { pci1_regions, pci2_regions }; 119 #endif 120 121 /* initialize the PCA9555PW IO expander on the PIB board */ 122 pib_init(); 123 124 #if defined(CONFIG_PCI_66M) 125 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; 126 printf("PCI clock is 66MHz\n"); 127 #elif defined(CONFIG_PCI_33M) 128 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | 129 OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; 130 printf("PCI clock is 33MHz\n"); 131 #else 132 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; 133 printf("PCI clock is 66MHz\n"); 134 #endif 135 udelay(2000); 136 137 /* Configure PCI Local Access Windows */ 138 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 139 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; 140 141 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 142 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; 143 144 udelay(2000); 145 146 #ifndef CONFIG_MPC83XX_PCI2 147 mpc83xx_pci_init(1, reg); 148 #else 149 mpc83xx_pci_init(2, reg); 150 #endif 151 } 152 #endif /* CONFIG_PCISLAVE */ 153