1 /* 2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * PCI Configuration space access support for MPC83xx PCI Bridge 9 */ 10 #include <asm/mmu.h> 11 #include <asm/io.h> 12 #include <common.h> 13 #include <mpc83xx.h> 14 #include <pci.h> 15 #include <i2c.h> 16 #include <asm/fsl_i2c.h> 17 #include "../common/pq-mds-pib.h" 18 19 static struct pci_region pci1_regions[] = { 20 { 21 bus_start: CONFIG_SYS_PCI1_MEM_BASE, 22 phys_start: CONFIG_SYS_PCI1_MEM_PHYS, 23 size: CONFIG_SYS_PCI1_MEM_SIZE, 24 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 25 }, 26 { 27 bus_start: CONFIG_SYS_PCI1_IO_BASE, 28 phys_start: CONFIG_SYS_PCI1_IO_PHYS, 29 size: CONFIG_SYS_PCI1_IO_SIZE, 30 flags: PCI_REGION_IO 31 }, 32 { 33 bus_start: CONFIG_SYS_PCI1_MMIO_BASE, 34 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, 35 size: CONFIG_SYS_PCI1_MMIO_SIZE, 36 flags: PCI_REGION_MEM 37 }, 38 }; 39 40 #ifdef CONFIG_MPC83XX_PCI2 41 static struct pci_region pci2_regions[] = { 42 { 43 bus_start: CONFIG_SYS_PCI2_MEM_BASE, 44 phys_start: CONFIG_SYS_PCI2_MEM_PHYS, 45 size: CONFIG_SYS_PCI2_MEM_SIZE, 46 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 47 }, 48 { 49 bus_start: CONFIG_SYS_PCI2_IO_BASE, 50 phys_start: CONFIG_SYS_PCI2_IO_PHYS, 51 size: CONFIG_SYS_PCI2_IO_SIZE, 52 flags: PCI_REGION_IO 53 }, 54 { 55 bus_start: CONFIG_SYS_PCI2_MMIO_BASE, 56 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, 57 size: CONFIG_SYS_PCI2_MMIO_SIZE, 58 flags: PCI_REGION_MEM 59 }, 60 }; 61 #endif 62 63 void pci_init_board(void) 64 #ifdef CONFIG_PCISLAVE 65 { 66 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 67 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 68 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; 69 struct pci_region *reg[] = { pci1_regions }; 70 71 /* Configure PCI Local Access Windows */ 72 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 73 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; 74 75 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 76 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; 77 78 mpc83xx_pci_init(1, reg); 79 80 /* 81 * Configure PCI Inbound Translation Windows 82 */ 83 pci_ctrl[0].pitar0 = 0x0; 84 pci_ctrl[0].pibar0 = 0x0; 85 pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | 86 PIWAR_WTT_SNOOP | PIWAR_IWS_4K; 87 88 pci_ctrl[0].pitar1 = 0x0; 89 pci_ctrl[0].pibar1 = 0x0; 90 pci_ctrl[0].piebar1 = 0x0; 91 pci_ctrl[0].piwar1 &= ~PIWAR_EN; 92 93 pci_ctrl[0].pitar2 = 0x0; 94 pci_ctrl[0].pibar2 = 0x0; 95 pci_ctrl[0].piebar2 = 0x0; 96 pci_ctrl[0].piwar2 &= ~PIWAR_EN; 97 98 /* Unlock the configuration bit */ 99 mpc83xx_pcislave_unlock(0); 100 printf("PCI: Agent mode enabled\n"); 101 } 102 #else 103 { 104 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 105 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 106 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 107 #ifndef CONFIG_MPC83XX_PCI2 108 struct pci_region *reg[] = { pci1_regions }; 109 #else 110 struct pci_region *reg[] = { pci1_regions, pci2_regions }; 111 #endif 112 113 /* initialize the PCA9555PW IO expander on the PIB board */ 114 pib_init(); 115 116 #if defined(CONFIG_PCI_66M) 117 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; 118 printf("PCI clock is 66MHz\n"); 119 #elif defined(CONFIG_PCI_33M) 120 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | 121 OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; 122 printf("PCI clock is 33MHz\n"); 123 #else 124 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; 125 printf("PCI clock is 66MHz\n"); 126 #endif 127 udelay(2000); 128 129 /* Configure PCI Local Access Windows */ 130 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 131 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; 132 133 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 134 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; 135 136 udelay(2000); 137 138 #ifndef CONFIG_MPC83XX_PCI2 139 mpc83xx_pci_init(1, reg); 140 #else 141 mpc83xx_pci_init(2, reg); 142 #endif 143 } 144 #endif /* CONFIG_PCISLAVE */ 145