1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * 4 * Dave Liu <daveliu@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <ioports.h> 11 #include <mpc83xx.h> 12 #include <i2c.h> 13 #include <miiphy.h> 14 #include <command.h> 15 #if defined(CONFIG_PCI) 16 #include <pci.h> 17 #endif 18 #include <asm/mmu.h> 19 #if defined(CONFIG_OF_LIBFDT) 20 #include <libfdt.h> 21 #endif 22 #if defined(CONFIG_PQ_MDS_PIB) 23 #include "../common/pq-mds-pib.h" 24 #endif 25 26 const qe_iop_conf_t qe_iop_conf_tab[] = { 27 /* ETH3 */ 28 {1, 0, 1, 0, 1}, /* TxD0 */ 29 {1, 1, 1, 0, 1}, /* TxD1 */ 30 {1, 2, 1, 0, 1}, /* TxD2 */ 31 {1, 3, 1, 0, 1}, /* TxD3 */ 32 {1, 9, 1, 0, 1}, /* TxER */ 33 {1, 12, 1, 0, 1}, /* TxEN */ 34 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ 35 36 {1, 4, 2, 0, 1}, /* RxD0 */ 37 {1, 5, 2, 0, 1}, /* RxD1 */ 38 {1, 6, 2, 0, 1}, /* RxD2 */ 39 {1, 7, 2, 0, 1}, /* RxD3 */ 40 {1, 8, 2, 0, 1}, /* RxER */ 41 {1, 10, 2, 0, 1}, /* RxDV */ 42 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ 43 {1, 11, 2, 0, 1}, /* COL */ 44 {1, 13, 2, 0, 1}, /* CRS */ 45 46 /* ETH4 */ 47 {1, 18, 1, 0, 1}, /* TxD0 */ 48 {1, 19, 1, 0, 1}, /* TxD1 */ 49 {1, 20, 1, 0, 1}, /* TxD2 */ 50 {1, 21, 1, 0, 1}, /* TxD3 */ 51 {1, 27, 1, 0, 1}, /* TxER */ 52 {1, 30, 1, 0, 1}, /* TxEN */ 53 {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ 54 55 {1, 22, 2, 0, 1}, /* RxD0 */ 56 {1, 23, 2, 0, 1}, /* RxD1 */ 57 {1, 24, 2, 0, 1}, /* RxD2 */ 58 {1, 25, 2, 0, 1}, /* RxD3 */ 59 {1, 26, 1, 0, 1}, /* RxER */ 60 {1, 28, 2, 0, 1}, /* Rx_DV */ 61 {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ 62 {1, 29, 2, 0, 1}, /* COL */ 63 {1, 31, 2, 0, 1}, /* CRS */ 64 65 {3, 4, 3, 0, 2}, /* MDIO */ 66 {3, 5, 1, 0, 2}, /* MDC */ 67 68 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 69 }; 70 71 int board_early_init_f(void) 72 { 73 volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR; 74 75 /* Enable flash write */ 76 bcsr[9] &= ~0x08; 77 78 return 0; 79 } 80 81 int board_early_init_r(void) 82 { 83 #ifdef CONFIG_PQ_MDS_PIB 84 pib_init(); 85 #endif 86 return 0; 87 } 88 89 int fixed_sdram(void); 90 91 phys_size_t initdram(int board_type) 92 { 93 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 94 u32 msize = 0; 95 96 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 97 return -1; 98 99 /* DDR SDRAM - Main SODIMM */ 100 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 101 102 msize = fixed_sdram(); 103 104 /* return total bus SDRAM size(bytes) -- DDR */ 105 return (msize * 1024 * 1024); 106 } 107 108 /************************************************************************* 109 * fixed sdram init -- doesn't use serial presence detect. 110 ************************************************************************/ 111 int fixed_sdram(void) 112 { 113 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 114 u32 msize = 0; 115 u32 ddr_size; 116 u32 ddr_size_log2; 117 118 msize = CONFIG_SYS_DDR_SIZE; 119 for (ddr_size = msize << 20, ddr_size_log2 = 0; 120 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { 121 if (ddr_size & 1) { 122 return -1; 123 } 124 } 125 im->sysconf.ddrlaw[0].ar = 126 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 127 #if (CONFIG_SYS_DDR_SIZE != 128) 128 #warning Currenly any ddr size other than 128 is not supported 129 #endif 130 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; 131 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; 132 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; 133 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 134 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 135 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 136 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 137 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; 138 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; 139 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 140 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; 141 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 142 __asm__ __volatile__ ("sync"); 143 udelay(200); 144 145 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 146 __asm__ __volatile__ ("sync"); 147 return msize; 148 } 149 150 int checkboard(void) 151 { 152 puts("Board: Freescale MPC832XEMDS\n"); 153 return 0; 154 } 155 156 #if defined(CONFIG_OF_BOARD_SETUP) 157 int ft_board_setup(void *blob, bd_t *bd) 158 { 159 ft_cpu_setup(blob, bd); 160 #ifdef CONFIG_PCI 161 ft_pci_setup(blob, bd); 162 #endif 163 164 return 0; 165 } 166 #endif 167