1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * 4 * Dave Liu <daveliu@freescale.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15 #include <common.h> 16 #include <ioports.h> 17 #include <mpc83xx.h> 18 #include <i2c.h> 19 #include <spd.h> 20 #include <miiphy.h> 21 #include <command.h> 22 #if defined(CONFIG_PCI) 23 #include <pci.h> 24 #endif 25 #if defined(CONFIG_SPD_EEPROM) 26 #include <spd_sdram.h> 27 #else 28 #include <asm/mmu.h> 29 #endif 30 #if defined(CONFIG_OF_FLAT_TREE) 31 #include <ft_build.h> 32 #elif defined(CONFIG_OF_LIBFDT) 33 #include <libfdt.h> 34 #endif 35 #if defined(CONFIG_PQ_MDS_PIB) 36 #include "../common/pq-mds-pib.h" 37 #endif 38 39 const qe_iop_conf_t qe_iop_conf_tab[] = { 40 /* ETH3 */ 41 {1, 0, 1, 0, 1}, /* TxD0 */ 42 {1, 1, 1, 0, 1}, /* TxD1 */ 43 {1, 2, 1, 0, 1}, /* TxD2 */ 44 {1, 3, 1, 0, 1}, /* TxD3 */ 45 {1, 9, 1, 0, 1}, /* TxER */ 46 {1, 12, 1, 0, 1}, /* TxEN */ 47 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ 48 49 {1, 4, 2, 0, 1}, /* RxD0 */ 50 {1, 5, 2, 0, 1}, /* RxD1 */ 51 {1, 6, 2, 0, 1}, /* RxD2 */ 52 {1, 7, 2, 0, 1}, /* RxD3 */ 53 {1, 8, 2, 0, 1}, /* RxER */ 54 {1, 10, 2, 0, 1}, /* RxDV */ 55 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ 56 {1, 11, 2, 0, 1}, /* COL */ 57 {1, 13, 2, 0, 1}, /* CRS */ 58 59 /* ETH4 */ 60 {1, 18, 1, 0, 1}, /* TxD0 */ 61 {1, 19, 1, 0, 1}, /* TxD1 */ 62 {1, 20, 1, 0, 1}, /* TxD2 */ 63 {1, 21, 1, 0, 1}, /* TxD3 */ 64 {1, 27, 1, 0, 1}, /* TxER */ 65 {1, 30, 1, 0, 1}, /* TxEN */ 66 {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ 67 68 {1, 22, 2, 0, 1}, /* RxD0 */ 69 {1, 23, 2, 0, 1}, /* RxD1 */ 70 {1, 24, 2, 0, 1}, /* RxD2 */ 71 {1, 25, 2, 0, 1}, /* RxD3 */ 72 {1, 26, 1, 0, 1}, /* RxER */ 73 {1, 28, 2, 0, 1}, /* Rx_DV */ 74 {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ 75 {1, 29, 2, 0, 1}, /* COL */ 76 {1, 31, 2, 0, 1}, /* CRS */ 77 78 {3, 4, 3, 0, 2}, /* MDIO */ 79 {3, 5, 1, 0, 2}, /* MDC */ 80 81 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 82 }; 83 84 int board_early_init_f(void) 85 { 86 volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; 87 88 /* Enable flash write */ 89 bcsr[9] &= ~0x08; 90 91 return 0; 92 } 93 94 int board_early_init_r(void) 95 { 96 #ifdef CONFIG_PQ_MDS_PIB 97 pib_init(); 98 #endif 99 return 0; 100 } 101 102 int fixed_sdram(void); 103 104 long int initdram(int board_type) 105 { 106 volatile immap_t *im = (immap_t *) CFG_IMMR; 107 u32 msize = 0; 108 109 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 110 return -1; 111 112 /* DDR SDRAM - Main SODIMM */ 113 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; 114 115 msize = fixed_sdram(); 116 117 /* return total bus SDRAM size(bytes) -- DDR */ 118 return (msize * 1024 * 1024); 119 } 120 121 /************************************************************************* 122 * fixed sdram init -- doesn't use serial presence detect. 123 ************************************************************************/ 124 int fixed_sdram(void) 125 { 126 volatile immap_t *im = (immap_t *) CFG_IMMR; 127 u32 msize = 0; 128 u32 ddr_size; 129 u32 ddr_size_log2; 130 131 msize = CFG_DDR_SIZE; 132 for (ddr_size = msize << 20, ddr_size_log2 = 0; 133 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { 134 if (ddr_size & 1) { 135 return -1; 136 } 137 } 138 im->sysconf.ddrlaw[0].ar = 139 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 140 #if (CFG_DDR_SIZE != 128) 141 #warning Currenly any ddr size other than 128 is not supported 142 #endif 143 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; 144 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; 145 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; 146 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 147 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 148 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 149 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 150 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 151 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 152 im->ddr.sdram_mode = CFG_DDR_MODE; 153 im->ddr.sdram_mode2 = CFG_DDR_MODE2; 154 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 155 __asm__ __volatile__ ("sync"); 156 udelay(200); 157 158 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 159 __asm__ __volatile__ ("sync"); 160 return msize; 161 } 162 163 int checkboard(void) 164 { 165 puts("Board: Freescale MPC832XEMDS\n"); 166 return 0; 167 } 168 169 #if defined(CONFIG_OF_BOARD_SETUP) 170 void ft_board_setup(void *blob, bd_t *bd) 171 { 172 #if defined(CONFIG_OF_FLAT_TREE) 173 u32 *p; 174 int len; 175 176 p = ft_get_prop(blob, "/memory/reg", &len); 177 if (p != NULL) { 178 *p++ = cpu_to_be32(bd->bi_memstart); 179 *p = cpu_to_be32(bd->bi_memsize); 180 } 181 #endif 182 ft_cpu_setup(blob, bd); 183 #ifdef CONFIG_PCI 184 ft_pci_setup(blob, bd); 185 #endif 186 } 187 #endif 188